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pull/45/head
Sergey 4 years ago
parent
de0681a203
commit
ffee9fd1be
5 changed files with 48 additions and 30 deletions
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  1. 8
      Marlin/Configuration.h
  2. 18
      Marlin/src/module/mks_wifi/mks_wifi_sd.cpp
  3. 1
      Marlin/src/module/mks_wifi/mks_wifi_sd.h
  4. 18
      Marlin/src/module/mks_wifi/small_cmsis.h
  5. 31
      Marlin/src/pins/stm32f1/pins_MKS_ROBIN_NANO.h

8
Marlin/Configuration.h
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@ -2639,10 +2639,10 @@ EEPROM_W25Q
#define TOUCH_SCREEN_CALIBRATION #define TOUCH_SCREEN_CALIBRATION
//#define TOUCH_CALIBRATION_X 12316 #define TOUCH_CALIBRATION_X XPT2046_X_CALIBRATION
//#define TOUCH_CALIBRATION_Y -8981 #define TOUCH_CALIBRATION_Y XPT2046_Y_CALIBRATION
//#define TOUCH_OFFSET_X -43 #define TOUCH_OFFSET_X XPT2046_X_OFFSET
//#define TOUCH_OFFSET_Y 257 #define TOUCH_OFFSET_Y XPT2046_Y_OFFSET
//#define TOUCH_ORIENTATION TOUCH_LANDSCAPE //#define TOUCH_ORIENTATION TOUCH_LANDSCAPE
#if BOTH(TOUCH_SCREEN_CALIBRATION, EEPROM_SETTINGS) #if BOTH(TOUCH_SCREEN_CALIBRATION, EEPROM_SETTINGS)

18
Marlin/src/module/mks_wifi/mks_wifi_sd.cpp
View File

@ -179,12 +179,12 @@ void mks_wifi_start_file_upload(ESP_PROTOC_FRAME *packet){
*/ */
safe_delay(200); safe_delay(200);
DMA1_Channel5->CCR = DMA_CCR_PL|DMA_CCR_MINC; DMA1_Channel5->CCR = DMA_N_CCR_PL|DMA_N_CCR_MINC;
DMA1_Channel5->CPAR = (uint32_t)&USART1->DR; DMA1_Channel5->CPAR = (uint32_t)&USART1->DR;
DMA1_Channel5->CMAR = (uint32_t)dma_buff[dma_buff_index]; DMA1_Channel5->CMAR = (uint32_t)dma_buff[dma_buff_index];
DMA1_Channel5->CNDTR = ESP_PACKET_SIZE; DMA1_Channel5->CNDTR = ESP_PACKET_SIZE;
DMA1_N->IFCR = DMA_IFCR_CGIF5|DMA_IFCR_CTEIF5|DMA_IFCR_CHTIF5|DMA_IFCR_CTCIF5; DMA1_N->IFCR = DMA_N_IFCR_CGIF5|DMA_N_IFCR_CTEIF5|DMA_N_IFCR_CHTIF5|DMA_N_IFCR_CTCIF5;
DMA1_Channel5->CCR |= DMA_CCR_EN; DMA1_Channel5->CCR |= DMA_N_CCR_EN;
file_inc_size=0; //Счетчик принятых данных, для записи в файл file_inc_size=0; //Счетчик принятых данных, для записи в файл
@ -201,8 +201,8 @@ void mks_wifi_start_file_upload(ESP_PROTOC_FRAME *packet){
iwdg_feed(); iwdg_feed();
if(DMA1_N->ISR & DMA_ISR_TCIF5){ if(DMA1_N->ISR & DMA_N_ISR_TCIF5){
DMA1_N->IFCR = DMA_IFCR_CGIF5|DMA_IFCR_CTEIF5|DMA_IFCR_CHTIF5|DMA_IFCR_CTCIF5; DMA1_N->IFCR = DMA_N_IFCR_CGIF5|DMA_N_IFCR_CTEIF5|DMA_N_IFCR_CHTIF5|DMA_N_IFCR_CTCIF5;
//Указатель на полученный буфер //Указатель на полученный буфер
buff=dma_buff[dma_buff_index]; buff=dma_buff[dma_buff_index];
@ -210,11 +210,11 @@ void mks_wifi_start_file_upload(ESP_PROTOC_FRAME *packet){
dma_buff_index = (dma_buff_index) ? 0 : 1; dma_buff_index = (dma_buff_index) ? 0 : 1;
//Запустить DMA на прием следующего пакета, пока обрабатывается этот //Запустить DMA на прием следующего пакета, пока обрабатывается этот
DMA1_Channel5->CCR = DMA_CCR_PL|DMA_CCR_MINC; DMA1_Channel5->CCR = DMA_N_CCR_PL|DMA_N_CCR_MINC;
DMA1_Channel5->CPAR = (uint32_t)&USART1->DR; DMA1_Channel5->CPAR = (uint32_t)&USART1->DR;
DMA1_Channel5->CMAR = (uint32_t)dma_buff[dma_buff_index]; DMA1_Channel5->CMAR = (uint32_t)dma_buff[dma_buff_index];
DMA1_Channel5->CNDTR = ESP_PACKET_SIZE; DMA1_Channel5->CNDTR = ESP_PACKET_SIZE;
DMA1_Channel5->CCR |= DMA_CCR_EN; DMA1_Channel5->CCR |= DMA_N_CCR_EN;
if(*buff != ESP_PROTOC_HEAD){ if(*buff != ESP_PROTOC_HEAD){
ERROR("Wrong packet head"); ERROR("Wrong packet head");
@ -315,7 +315,7 @@ void mks_wifi_start_file_upload(ESP_PROTOC_FRAME *packet){
dma_timeout = DMA_TIMEOUT; dma_timeout = DMA_TIMEOUT;
} }
if(DMA1_N->ISR & DMA_ISR_TEIF5){ if(DMA1_N->ISR & DMA_N_ISR_TEIF5){
ERROR("DMA Error"); ERROR("DMA Error");
} }
@ -323,7 +323,7 @@ void mks_wifi_start_file_upload(ESP_PROTOC_FRAME *packet){
//Выключить DMA //Выключить DMA
DMA1_N->IFCR = DMA_IFCR_CGIF5|DMA_IFCR_CTEIF5|DMA_IFCR_CHTIF5|DMA_IFCR_CTCIF5; DMA1_N->IFCR = DMA_N_IFCR_CGIF5|DMA_N_IFCR_CTEIF5|DMA_N_IFCR_CHTIF5|DMA_N_IFCR_CTCIF5;
DMA1_Channel5->CCR = 0; DMA1_Channel5->CCR = 0;
//Восстановить USART1 //Восстановить USART1

1
Marlin/src/module/mks_wifi/mks_wifi_sd.h
View File

@ -3,7 +3,6 @@
#include "mks_wifi.h" #include "mks_wifi.h"
#include "../../sd/cardreader.h" #include "../../sd/cardreader.h"
#include "small_cmsis.h" #include "small_cmsis.h"
#include "../shared_mem/shared_mem.h" #include "../shared_mem/shared_mem.h"
#ifdef MKS_WIFI #ifdef MKS_WIFI

18
Marlin/src/module/mks_wifi/small_cmsis.h
View File

@ -252,13 +252,13 @@ typedef struct
//#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */ //#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
#define DMA_ISR_TCIF5_Pos (17U) #define DMA_ISR_TCIF5_Pos (17U)
#define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */ #define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
//#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */ #define DMA_N_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
#define DMA_ISR_HTIF5_Pos (18U) #define DMA_ISR_HTIF5_Pos (18U)
#define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */ #define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
//#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */ //#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
#define DMA_ISR_TEIF5_Pos (19U) #define DMA_ISR_TEIF5_Pos (19U)
#define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */ #define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
//#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */ #define DMA_N_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
#define DMA_ISR_GIF6_Pos (20U) #define DMA_ISR_GIF6_Pos (20U)
#define DMA_ISR_GIF6_Msk (0x1U << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */ #define DMA_ISR_GIF6_Msk (0x1U << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
//#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */ //#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
@ -336,16 +336,16 @@ typedef struct
#define DMA_N_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */ #define DMA_N_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
#define DMA_IFCR_CGIF5_Pos (16U) #define DMA_IFCR_CGIF5_Pos (16U)
#define DMA_IFCR_CGIF5_Msk (0x1U << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */ #define DMA_IFCR_CGIF5_Msk (0x1U << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
//#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */ #define DMA_N_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
#define DMA_IFCR_CTCIF5_Pos (17U) #define DMA_IFCR_CTCIF5_Pos (17U)
#define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */ #define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
//#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */ #define DMA_N_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
#define DMA_IFCR_CHTIF5_Pos (18U) #define DMA_IFCR_CHTIF5_Pos (18U)
#define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */ #define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
//#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */ #define DMA_N_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
#define DMA_IFCR_CTEIF5_Pos (19U) #define DMA_IFCR_CTEIF5_Pos (19U)
#define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */ #define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
//#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */ #define DMA_N_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
#define DMA_IFCR_CGIF6_Pos (20U) #define DMA_IFCR_CGIF6_Pos (20U)
#define DMA_IFCR_CGIF6_Msk (0x1U << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */ #define DMA_IFCR_CGIF6_Msk (0x1U << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
//#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */ //#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
@ -375,7 +375,7 @@ typedef struct
/******************* Bit definition for DMA_CCR register *******************/ /******************* Bit definition for DMA_CCR register *******************/
#define DMA_CCR_EN_Pos (0U) #define DMA_CCR_EN_Pos (0U)
#define DMA_CCR_EN_Msk (0x1U << DMA_CCR_EN_Pos) /*!< 0x00000001 */ #define DMA_CCR_EN_Msk (0x1U << DMA_CCR_EN_Pos) /*!< 0x00000001 */
//#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */ #define DMA_N_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
#define DMA_CCR_TCIE_Pos (1U) #define DMA_CCR_TCIE_Pos (1U)
#define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */ #define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
//#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */ //#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
@ -396,7 +396,7 @@ typedef struct
//#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */ //#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
#define DMA_CCR_MINC_Pos (7U) #define DMA_CCR_MINC_Pos (7U)
#define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /*!< 0x00000080 */ #define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
//#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */ #define DMA_N_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
#define DMA_CCR_PSIZE_Pos (8U) #define DMA_CCR_PSIZE_Pos (8U)
#define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */ #define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
@ -412,7 +412,7 @@ typedef struct
#define DMA_CCR_PL_Pos (12U) #define DMA_CCR_PL_Pos (12U)
#define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /*!< 0x00003000 */ #define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /*!< 0x00003000 */
//#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level) */ #define DMA_N_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level) */
#define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */ #define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */
#define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */ #define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */

31
Marlin/src/pins/stm32f1/pins_MKS_ROBIN_NANO.h
View File

@ -140,13 +140,17 @@ BlTouch
/* /*
Управление питанием Управление питанием
https://sergey1560.github.io/fb4s_howto/mks_pwc/
*/ */
//#define SUICIDE_PIN PE5 //#define MKS_PWC
//#define SUICIDE_PIN_INVERTING false
//#define PLR_PIN PA2 // PW_DET
//#define KILL_PIN PA2 // Enable MKSPWC DET PIN
//#define KILL_PIN_STATE true // Enable MKSPWC PIN STATE
#ifdef MKS_PWC
#define SUICIDE_PIN PE5
#define SUICIDE_PIN_INVERTING false
#define PLR_PIN PA2 // PW_DET
#define KILL_PIN PA2 // Enable MKSPWC DET PIN
#define KILL_PIN_STATE true // Enable MKSPWC PIN STATE
#endif
// //
// Thermocouples // Thermocouples
@ -188,7 +192,7 @@ BlTouch
#endif #endif
#define SDIO_SUPPORT #define SDIO_SUPPORT
#define SDIO_CLOCK 18000000 // 4.5 MHz #define SDIO_CLOCK 18000000
#define SD_DETECT_PIN PD12 #define SD_DETECT_PIN PD12
#define ONBOARD_SD_CS_PIN PC11 #define ONBOARD_SD_CS_PIN PC11
@ -255,6 +259,21 @@ BlTouch
#define MKS_WIFI_IO_RST PA5 #define MKS_WIFI_IO_RST PA5
#endif #endif
#ifndef XPT2046_X_CALIBRATION
#define XPT2046_X_CALIBRATION 17880
#endif
#ifndef XPT2046_Y_CALIBRATION
#define XPT2046_Y_CALIBRATION -12234
#endif
#ifndef XPT2046_X_OFFSET
#define XPT2046_X_OFFSET -45
#endif
#ifndef XPT2046_Y_OFFSET
#define XPT2046_Y_OFFSET 349
#endif
#if HAS_TMC220x #if HAS_TMC220x
/** /**
* TMC2208/TMC2209 stepper drivers * TMC2208/TMC2209 stepper drivers

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