|
|
@ -581,12 +581,35 @@ |
|
|
|
// --------------------------------------------------------------------------
|
|
|
|
// hardware SPI
|
|
|
|
// --------------------------------------------------------------------------
|
|
|
|
static bool spiInitialized = false; |
|
|
|
|
|
|
|
void spiInit(uint8_t spiRate) { |
|
|
|
if (spiInitialized) return; |
|
|
|
|
|
|
|
// 8.4 MHz, 4 MHz, 2 MHz, 1 MHz, 0.5 MHz, 0.329 MHz, 0.329 MHz
|
|
|
|
int spiDueDividors[] = { 10, 21, 42, 84, 168, 255, 255 }; |
|
|
|
bool spiInitMaded = false; |
|
|
|
constexpr int spiDivider[] = { 10, 21, 42, 84, 168, 255, 255 }; |
|
|
|
if (spiRate > 6) spiRate = 1; |
|
|
|
|
|
|
|
// Set SPI mode 1, clock, select not active after transfer, with delay between transfers
|
|
|
|
SPI_ConfigureNPCS(SPI0, SPI_CHAN_DAC, |
|
|
|
SPI_CSR_CSAAT | SPI_CSR_SCBR(spiDivider[spiRate]) | |
|
|
|
SPI_CSR_DLYBCT(1)); |
|
|
|
// Set SPI mode 0, clock, select not active after transfer, with delay between transfers
|
|
|
|
SPI_ConfigureNPCS(SPI0, SPI_CHAN_EEPROM1, SPI_CSR_NCPHA | |
|
|
|
SPI_CSR_CSAAT | SPI_CSR_SCBR(spiDivider[spiRate]) | |
|
|
|
SPI_CSR_DLYBCT(1)); |
|
|
|
|
|
|
|
// Set SPI mode 0, clock, select not active after transfer, with delay between transfers
|
|
|
|
SPI_ConfigureNPCS(SPI0, SPI_CHAN, SPI_CSR_NCPHA | |
|
|
|
SPI_CSR_CSAAT | SPI_CSR_SCBR(spiDivider[spiRate]) | |
|
|
|
SPI_CSR_DLYBCT(1)); |
|
|
|
SPI_Enable(SPI0); |
|
|
|
spiInitialized = true; |
|
|
|
} |
|
|
|
|
|
|
|
void spiBegin() { |
|
|
|
if (spiInitMaded == false) { |
|
|
|
if (spiInitialized) return; |
|
|
|
|
|
|
|
// Configure SPI pins
|
|
|
|
PIO_Configure( |
|
|
|
g_APinDescription[SCK_PIN].pPort, |
|
|
@ -608,7 +631,6 @@ |
|
|
|
SPI_Configure(SPI0, ID_SPI0, SPI_MR_MSTR | SPI_MR_MODFDIS | SPI_MR_PS); |
|
|
|
SPI_Enable(SPI0); |
|
|
|
|
|
|
|
#if MB(ALLIGATOR) |
|
|
|
SET_OUTPUT(DAC0_SYNC); |
|
|
|
#if EXTRUDERS > 1 |
|
|
|
SET_OUTPUT(DAC1_SYNC); |
|
|
@ -622,7 +644,6 @@ |
|
|
|
WRITE(SPI_EEPROM2_CS, HIGH ); |
|
|
|
WRITE(SPI_FLASH_CS, HIGH ); |
|
|
|
WRITE(SS_PIN, HIGH ); |
|
|
|
#endif // MB(ALLIGATOR)
|
|
|
|
|
|
|
|
OUT_WRITE(SDSS,0); |
|
|
|
|
|
|
@ -633,32 +654,51 @@ |
|
|
|
g_APinDescription[SPI_PIN].ulPinConfiguration); |
|
|
|
|
|
|
|
spiInit(1); |
|
|
|
spiInitMaded = true; |
|
|
|
} |
|
|
|
|
|
|
|
// Read single byte from SPI
|
|
|
|
uint8_t spiRec() { |
|
|
|
// write dummy byte with address and end transmission flag
|
|
|
|
SPI0->SPI_TDR = 0x000000FF | SPI_PCS(SPI_CHAN) | SPI_TDR_LASTXFER; |
|
|
|
// wait for transmit register empty
|
|
|
|
while ((SPI0->SPI_SR & SPI_SR_TDRE) == 0); |
|
|
|
|
|
|
|
// wait for receive register
|
|
|
|
while ((SPI0->SPI_SR & SPI_SR_RDRF) == 0); |
|
|
|
// get byte from receive register
|
|
|
|
//DELAY_US(1U);
|
|
|
|
return SPI0->SPI_RDR; |
|
|
|
} |
|
|
|
|
|
|
|
void spiInit(uint8_t spiRate) { |
|
|
|
if (spiInitMaded == false) { |
|
|
|
if (spiRate > 6) spiRate = 1; |
|
|
|
uint8_t spiRec(uint32_t chan) { |
|
|
|
uint8_t spirec_tmp; |
|
|
|
// wait for transmit register empty
|
|
|
|
while ((SPI0->SPI_SR & SPI_SR_TDRE) == 0); |
|
|
|
while ((SPI0->SPI_SR & SPI_SR_RDRF) == 1) |
|
|
|
spirec_tmp = SPI0->SPI_RDR; |
|
|
|
UNUSED(spirec_tmp); |
|
|
|
|
|
|
|
#if MB(ALLIGATOR) |
|
|
|
// Set SPI mode 1, clock, select not active after transfer, with delay between transfers
|
|
|
|
SPI_ConfigureNPCS(SPI0, SPI_CHAN_DAC, |
|
|
|
SPI_CSR_CSAAT | SPI_CSR_SCBR(spiDueDividors[spiRate]) | |
|
|
|
SPI_CSR_DLYBCT(1)); |
|
|
|
// Set SPI mode 0, clock, select not active after transfer, with delay between transfers
|
|
|
|
SPI_ConfigureNPCS(SPI0, SPI_CHAN_EEPROM1, SPI_CSR_NCPHA | |
|
|
|
SPI_CSR_CSAAT | SPI_CSR_SCBR(spiDueDividors[spiRate]) | |
|
|
|
SPI_CSR_DLYBCT(1)); |
|
|
|
#endif//MB(ALLIGATOR)
|
|
|
|
// write dummy byte with address and end transmission flag
|
|
|
|
SPI0->SPI_TDR = 0x000000FF | SPI_PCS(chan) | SPI_TDR_LASTXFER; |
|
|
|
|
|
|
|
// Set SPI mode 0, clock, select not active after transfer, with delay between transfers
|
|
|
|
SPI_ConfigureNPCS(SPI0, SPI_CHAN, SPI_CSR_NCPHA | |
|
|
|
SPI_CSR_CSAAT | SPI_CSR_SCBR(spiDueDividors[spiRate]) | |
|
|
|
SPI_CSR_DLYBCT(1)); |
|
|
|
SPI_Enable(SPI0); |
|
|
|
spiInitMaded = true; |
|
|
|
// wait for receive register
|
|
|
|
while ((SPI0->SPI_SR & SPI_SR_RDRF) == 0); |
|
|
|
// get byte from receive register
|
|
|
|
return SPI0->SPI_RDR; |
|
|
|
} |
|
|
|
|
|
|
|
// Read from SPI into buffer
|
|
|
|
void spiRead(uint8_t* buf, uint16_t nbyte) { |
|
|
|
if (nbyte-- == 0) return; |
|
|
|
|
|
|
|
for (int i = 0; i < nbyte; i++) { |
|
|
|
//while ((SPI0->SPI_SR & SPI_SR_TDRE) == 0);
|
|
|
|
SPI0->SPI_TDR = 0x000000FF | SPI_PCS(SPI_CHAN); |
|
|
|
while ((SPI0->SPI_SR & SPI_SR_RDRF) == 0); |
|
|
|
buf[i] = SPI0->SPI_RDR; |
|
|
|
//DELAY_US(1U);
|
|
|
|
} |
|
|
|
buf[nbyte] = spiRec(); |
|
|
|
} |
|
|
|
|
|
|
|
// Write single byte to SPI
|
|
|
@ -714,51 +754,6 @@ |
|
|
|
spiSend(chan, buf[n - 1]); |
|
|
|
} |
|
|
|
|
|
|
|
// Read single byte from SPI
|
|
|
|
uint8_t spiRec() { |
|
|
|
// write dummy byte with address and end transmission flag
|
|
|
|
SPI0->SPI_TDR = 0x000000FF | SPI_PCS(SPI_CHAN) | SPI_TDR_LASTXFER; |
|
|
|
// wait for transmit register empty
|
|
|
|
while ((SPI0->SPI_SR & SPI_SR_TDRE) == 0); |
|
|
|
|
|
|
|
// wait for receive register
|
|
|
|
while ((SPI0->SPI_SR & SPI_SR_RDRF) == 0); |
|
|
|
// get byte from receive register
|
|
|
|
//DELAY_US(1U);
|
|
|
|
return SPI0->SPI_RDR; |
|
|
|
} |
|
|
|
|
|
|
|
uint8_t spiRec(uint32_t chan) { |
|
|
|
uint8_t spirec_tmp; |
|
|
|
// wait for transmit register empty
|
|
|
|
while ((SPI0->SPI_SR & SPI_SR_TDRE) == 0); |
|
|
|
while ((SPI0->SPI_SR & SPI_SR_RDRF) == 1) |
|
|
|
spirec_tmp = SPI0->SPI_RDR; |
|
|
|
UNUSED(spirec_tmp); |
|
|
|
|
|
|
|
// write dummy byte with address and end transmission flag
|
|
|
|
SPI0->SPI_TDR = 0x000000FF | SPI_PCS(chan) | SPI_TDR_LASTXFER; |
|
|
|
|
|
|
|
// wait for receive register
|
|
|
|
while ((SPI0->SPI_SR & SPI_SR_RDRF) == 0); |
|
|
|
// get byte from receive register
|
|
|
|
return SPI0->SPI_RDR; |
|
|
|
} |
|
|
|
|
|
|
|
// Read from SPI into buffer
|
|
|
|
void spiRead(uint8_t* buf, uint16_t nbyte) { |
|
|
|
if (nbyte-- == 0) return; |
|
|
|
|
|
|
|
for (int i = 0; i < nbyte; i++) { |
|
|
|
//while ((SPI0->SPI_SR & SPI_SR_TDRE) == 0);
|
|
|
|
SPI0->SPI_TDR = 0x000000FF | SPI_PCS(SPI_CHAN); |
|
|
|
while ((SPI0->SPI_SR & SPI_SR_RDRF) == 0); |
|
|
|
buf[i] = SPI0->SPI_RDR; |
|
|
|
//DELAY_US(1U);
|
|
|
|
} |
|
|
|
buf[nbyte] = spiRec(); |
|
|
|
} |
|
|
|
|
|
|
|
// Write from buffer to SPI
|
|
|
|
void spiSendBlock(uint8_t token, const uint8_t* buf) { |
|
|
|
SPI0->SPI_TDR = (uint32_t)token | SPI_PCS(SPI_CHAN); |
|
|
@ -789,7 +784,7 @@ |
|
|
|
|
|
|
|
void spiInit(uint8_t spiRate=6) { // Default to slowest rate if not specified)
|
|
|
|
// 8.4 MHz, 4 MHz, 2 MHz, 1 MHz, 0.5 MHz, 0.329 MHz, 0.329 MHz
|
|
|
|
int spiDueDividors[] = { 10, 21, 42, 84, 168, 255, 255 }; |
|
|
|
constexpr int spiDivider[] = { 10, 21, 42, 84, 168, 255, 255 }; |
|
|
|
if (spiRate > 6) spiRate = 1; |
|
|
|
|
|
|
|
// Enable PIOA and SPI0
|
|
|
@ -809,7 +804,11 @@ |
|
|
|
// Master mode, no fault detection, PCS bits in data written to TDR select CSR register
|
|
|
|
SPI0->SPI_MR = SPI_MR_MSTR | SPI_MR_PS | SPI_MR_MODFDIS; |
|
|
|
// SPI mode 0, 8 Bit data transfer, baud rate
|
|
|
|
SPI0->SPI_CSR[3] = SPI_CSR_SCBR(spiDueDividors[spiRate]) | SPI_CSR_CSAAT | SPI_MODE_0_DUE_HW; // use same CSR as TMC2130
|
|
|
|
SPI0->SPI_CSR[3] = SPI_CSR_SCBR(spiDivider[spiRate]) | SPI_CSR_CSAAT | SPI_MODE_0_DUE_HW; // use same CSR as TMC2130
|
|
|
|
} |
|
|
|
|
|
|
|
void spiBegin() { |
|
|
|
spiInit(); |
|
|
|
} |
|
|
|
|
|
|
|
static uint8_t spiTransfer(uint8_t data) { |
|
|
@ -828,10 +827,6 @@ |
|
|
|
return SPI0->SPI_RDR; |
|
|
|
} |
|
|
|
|
|
|
|
void spiBegin() { |
|
|
|
spiInit(); |
|
|
|
} |
|
|
|
|
|
|
|
uint8_t spiRec() { |
|
|
|
uint8_t data = spiTransfer(0xFF); |
|
|
|
return data; |
|
|
|