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@ -53,7 +53,7 @@ uint8_t SD_Cmd(uint8_t cmd, uint32_t arg, uint16_t response_type, uint32_t *resp |
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return 0; |
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return 0; |
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} |
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} |
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uint32_t SD_transfer(uint8_t *buf, uint32_t blk, uint32_t cnt, uint32_t dir){ |
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uint32_t __attribute__((optimize("O0"))) SD_transfer(uint8_t *buf, uint32_t blk, uint32_t cnt, uint32_t dir){ |
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uint32_t trials; |
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uint32_t trials; |
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uint8_t cmd=0; |
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uint8_t cmd=0; |
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@ -99,7 +99,7 @@ uint32_t SD_transfer(uint8_t *buf, uint32_t blk, uint32_t cnt, uint32_t dir){ |
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transmit=1; |
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transmit=1; |
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error_flag=0; |
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error_flag=0; |
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__disable_irq(); |
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//__disable_irq();
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SD_Cmd(cmd, blk, SDIO_RESP_SHORT, (uint32_t*)response); |
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SD_Cmd(cmd, blk, SDIO_RESP_SHORT, (uint32_t*)response); |
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SDIO->DTIMER=(uint32_t)SDIO_DATA_R_TIMEOUT; |
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SDIO->DTIMER=(uint32_t)SDIO_DATA_R_TIMEOUT; |
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@ -109,8 +109,9 @@ uint32_t SD_transfer(uint8_t *buf, uint32_t blk, uint32_t cnt, uint32_t dir){ |
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SDIO->ICR=SDIO_ICR_STATIC; |
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SDIO->ICR=SDIO_ICR_STATIC; |
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DMA2_Stream3->CR |= DMA_SxCR_EN; |
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DMA2_Stream3->CR |= DMA_SxCR_EN; |
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__DSB(); |
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SDIO->DCTRL|=1; //DPSM is enabled
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SDIO->DCTRL|=1; //DPSM is enabled
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__enable_irq(); |
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//__enable_irq();
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while((SDIO->STA & (SDIO_STA_DATAEND|SDIO_STA_ERRORS)) == 0){asm("nop");}; |
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while((SDIO->STA & (SDIO_STA_DATAEND|SDIO_STA_ERRORS)) == 0){asm("nop");}; |
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