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@ -53,7 +53,7 @@ |
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// Public functions
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// --------------------------------------------------------------------------
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#if ENABLED(DUE_SOFTWARE_SPI) |
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#if EITHER(DUE_SOFTWARE_SPI, FORCE_SOFT_SPI) |
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// --------------------------------------------------------------------------
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// software SPI
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@ -739,7 +739,42 @@ |
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#define SPI_MODE_2_DUE_HW 0 |
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#define SPI_MODE_3_DUE_HW 1 |
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/**
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* The DUE SPI controller is set up so the upper word of the longword |
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* written to the transmit data register selects which SPI Chip Select |
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* Register is used. This allows different streams to have different SPI |
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* settings. |
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* |
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* In practice it's spooky. Some combinations hang the system, while others |
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* upset the peripheral device. |
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* |
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* SPI mode should be the same for all streams. The FYSETC_MINI_12864 gets |
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* upset if the clock phase changes after chip select goes active. |
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* |
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* SPI_CSR_CSAAT should be set for all streams. If not the WHILE_TX(0) |
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* macro returns immediately which can result in the SPI chip select going |
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* inactive before all the data has been sent. |
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* |
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* The TMC2130 library uses SPI0->SPI_CSR[3]. |
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* |
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* The U8G hardware SPI uses SPI0->SPI_CSR[0]. The system hangs and/or the |
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* FYSETC_MINI_12864 gets upset if lower baud rates are used and the SD card |
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* is inserted or removed. |
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* |
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* The SD card uses SPI0->SPI_CSR[3]. Efforts were made to use [1] and [2] |
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* but they all resulted in hangs or garbage on the LCD. |
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* |
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* The SPI controlled chip selects are NOT enabled in the GPIO controller. |
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* The application must control the chip select. |
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* |
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* All of the above can be avoided by defining FORCE_SOFT_SPI to force the |
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* display to use software SPI. |
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* |
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*/ |
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void spiInit(uint8_t spiRate=6) { // Default to slowest rate if not specified)
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// Also sets U8G SPI rate to 4MHz and the SPI mode to 3
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// 8.4 MHz, 4 MHz, 2 MHz, 1 MHz, 0.5 MHz, 0.329 MHz, 0.329 MHz
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constexpr int spiDivider[] = { 10, 21, 42, 84, 168, 255, 255 }; |
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if (spiRate > 6) spiRate = 1; |
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@ -760,15 +795,16 @@ |
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// TMC2103 compatible setup
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// Master mode, no fault detection, PCS bits in data written to TDR select CSR register
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SPI0->SPI_MR = SPI_MR_MSTR | SPI_MR_PS | SPI_MR_MODFDIS; |
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// SPI mode 0, 8 Bit data transfer, baud rate
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SPI0->SPI_CSR[3] = SPI_CSR_SCBR(spiDivider[spiRate]) | SPI_CSR_CSAAT | SPI_MODE_0_DUE_HW; // use same CSR as TMC2130
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// SPI mode 3, 8 Bit data transfer, baud rate
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SPI0->SPI_CSR[3] = SPI_CSR_SCBR(spiDivider[spiRate]) | SPI_CSR_CSAAT | SPI_MODE_3_DUE_HW; // use same CSR as TMC2130
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SPI0->SPI_CSR[0] = SPI_CSR_SCBR(spiDivider[1]) | SPI_CSR_CSAAT | SPI_MODE_3_DUE_HW; // U8G default to 4MHz
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} |
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void spiBegin() { spiInit(); } |
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static uint8_t spiTransfer(uint8_t data) { |
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WHILE_TX(0); |
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SPI0->SPI_TDR = (uint32_t)data | 0x00070000UL; // Add TMC2130 PCS bits to every byte
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SPI0->SPI_TDR = (uint32_t)data | 0x00070000UL; // Add TMC2130 PCS bits to every byte (use SPI0->SPI_CSR[3])
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WHILE_TX(0); |
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WHILE_RX(0); |
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return SPI0->SPI_RDR; |
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Bob Kuhn
6 years ago
Scott Lahteine