🐛 Fix AVR DELAY_US int overflow (#22268)

Marlin/src/HAL/shared/Delay.h

@@ -97,43 +97,65 @@ void calibrate_delay_loop();
   #define DELAY_US(x) DelayCycleFnc((x) * ((F_CPU) / 1000000UL))
 
 #elif defined(__AVR__)
-
+  FORCE_INLINE static void __delay_up_to_3c(uint8_t cycles) {
-  #define nop() __asm__ __volatile__("nop;\n\t":::)
+    switch (cycles) {
-
+      case 3:
-  FORCE_INLINE static void __delay_4cycles(uint8_t cy) {
+        __asm__ __volatile__(A("RJMP .+0") A("NOP"));
-    __asm__ __volatile__(
+        break;
-      L("1")
+      case 2:
-      A("dec %[cnt]")
+        __asm__ __volatile__(A("RJMP .+0"));
-      A("nop")
+        break;
-      A("brne 1b")
+      case 1:
-      : [cnt] "+r"(cy)  // output: +r means input+output
+        __asm__ __volatile__(A("NOP"));
-      :                 // input:
+        break;
-      : "cc"            // clobbers:
+    }
-    );
   }
 
   // Delay in cycles
-  FORCE_INLINE static void DELAY_CYCLES(uint16_t x) {
+  FORCE_INLINE static void DELAY_CYCLES(uint16_t cycles) {
-
+    if (__builtin_constant_p(cycles)) {
-    if (__builtin_constant_p(x)) {
+      if (cycles <= 3) {
-      #define MAXNOPS 4
+        __delay_up_to_3c(cycles);
-
+      }
-      if (x <= (MAXNOPS)) {
+      else if (cycles == 4) {
-        switch (x) { case 4: nop(); case 3: nop(); case 2: nop(); case 1: nop(); }
+        __delay_up_to_3c(2);
+        __delay_up_to_3c(2);
       }
       else {
-        const uint32_t rem = (x) % (MAXNOPS);
+        cycles -= 1 + 4; // Compensate for the first LDI (1) and the first round (4)
-        switch (rem) { case 3: nop(); case 2: nop(); case 1: nop(); }
+        __delay_up_to_3c(cycles % 4);
-        if ((x = (x) / (MAXNOPS)))
+
-          __delay_4cycles(x); // if need more then 4 nop loop is more optimal
+        cycles /= 4;
+        // The following code burns [1 + 4 * (rounds+1)] cycles
+        uint16_t dummy;
+        __asm__ __volatile__(
+          // "manually" load counter from constants, otherwise the compiler may optimize this part away
+          A("LDI %A[rounds], %[l]") // 1c
+          A("LDI %B[rounds], %[h]") // 1c (compensating the non branching BRCC)
+          L("1")
+          A("SBIW %[rounds], 1")    // 2c
+          A("BRCC 1b")              // 2c when branching, else 1c (end of loop)
+          : // Outputs ...
+          [rounds] "=w" (dummy) // Restrict to a wo (=) 16 bit register pair (w)
+          : // Inputs ...
+          [l] "M" (cycles%256), // Restrict to 0..255 constant (M)
+          [h] "M" (cycles/256)  // Restrict to 0..255 constant (M)
+          :// Clobbers ...
+          "cc"                  // Indicate we are modifying flags like Carry (cc)
+        );
       }
-
-      #undef MAXNOPS
     }
-    else if ((x >>= 2))
+    else {
-      __delay_4cycles(x);
+      __asm__ __volatile__(
+        L("1")
+        A("SBIW %[cycles], 4")   // 2c
+        A("BRCC 1b")             // 2c when branching, else 1c (end of loop)
+        : [cycles] "+w" (cycles) // output: Restrict to a rw (+) 16 bit register pair (w)
+        :                        // input: -
+        : "cc"                   // clobbers: We are modifying flags like Carry (cc)
+      );
+    }
   }
-  #undef nop
 
   // Delay in microseconds
   #define DELAY_US(x) DELAY_CYCLES((x) * ((F_CPU) / 1000000UL))