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@ -168,8 +168,8 @@ static void initISR(timer16_Sequence_t timer) { |
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SBI(TIFR, OCF3A); // clear any pending interrupts;
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SBI(TIFR, OCF3A); // clear any pending interrupts;
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SBI(ETIMSK, OCIE3A); // enable the output compare interrupt
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SBI(ETIMSK, OCIE3A); // enable the output compare interrupt
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#else |
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#else |
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TIFR3 = _BV(OCF3A); // clear any pending interrupts;
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SBI(TIFR3, OCF3A); // clear any pending interrupts;
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TIMSK3 = _BV(OCIE3A) ; // enable the output compare interrupt
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SBI(TIMSK3, OCIE3A); // enable the output compare interrupt
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#endif |
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#endif |
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#ifdef WIRING |
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#ifdef WIRING |
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timerAttach(TIMER3OUTCOMPAREA_INT, Timer3Service); // for Wiring platform only
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timerAttach(TIMER3OUTCOMPAREA_INT, Timer3Service); // for Wiring platform only
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@ -183,7 +183,7 @@ static void initISR(timer16_Sequence_t timer) { |
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TCCR4B = _BV(CS41); // set prescaler of 8
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TCCR4B = _BV(CS41); // set prescaler of 8
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TCNT4 = 0; // clear the timer count
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TCNT4 = 0; // clear the timer count
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TIFR4 = _BV(OCF4A); // clear any pending interrupts;
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TIFR4 = _BV(OCF4A); // clear any pending interrupts;
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TIMSK4 = _BV(OCIE4A) ; // enable the output compare interrupt
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TIMSK4 = _BV(OCIE4A); // enable the output compare interrupt
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} |
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} |
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#endif |
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#endif |
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@ -193,7 +193,7 @@ static void initISR(timer16_Sequence_t timer) { |
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TCCR5B = _BV(CS51); // set prescaler of 8
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TCCR5B = _BV(CS51); // set prescaler of 8
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TCNT5 = 0; // clear the timer count
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TCNT5 = 0; // clear the timer count
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TIFR5 = _BV(OCF5A); // clear any pending interrupts;
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TIFR5 = _BV(OCF5A); // clear any pending interrupts;
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TIMSK5 = _BV(OCIE5A) ; // enable the output compare interrupt
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TIMSK5 = _BV(OCIE5A); // enable the output compare interrupt
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} |
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} |
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#endif |
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#endif |
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} |
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} |
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@ -203,21 +203,21 @@ static void finISR(timer16_Sequence_t timer) { |
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#ifdef WIRING |
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#ifdef WIRING |
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if (timer == _timer1) { |
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if (timer == _timer1) { |
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CBI( |
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CBI( |
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#if defined(__AVR_ATmega1281__) || defined(__AVR_ATmega2561__) |
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#if defined(__AVR_ATmega1281__) || defined(__AVR_ATmega2561__) |
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TIMSK1 |
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TIMSK1 |
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#else |
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#else |
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TIMSK |
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TIMSK |
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#endif |
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#endif |
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, OCIE1A); // disable timer 1 output compare interrupt
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, OCIE1A); // disable timer 1 output compare interrupt
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timerDetach(TIMER1OUTCOMPAREA_INT); |
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timerDetach(TIMER1OUTCOMPAREA_INT); |
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} |
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} |
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else if (timer == _timer3) { |
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else if (timer == _timer3) { |
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CBI( |
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CBI( |
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#if defined(__AVR_ATmega1281__) || defined(__AVR_ATmega2561__) |
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#if defined(__AVR_ATmega1281__) || defined(__AVR_ATmega2561__) |
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TIMSK3 |
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TIMSK3 |
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#else |
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#else |
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ETIMSK |
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ETIMSK |
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#endif |
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#endif |
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, OCIE3A); // disable the timer3 output compare A interrupt
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, OCIE3A); // disable the timer3 output compare A interrupt
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timerDetach(TIMER3OUTCOMPAREA_INT); |
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timerDetach(TIMER3OUTCOMPAREA_INT); |
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} |
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} |
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