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@ -33,18 +33,18 @@ |
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*/ |
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static bool isDataProc(uint32_t instr) { |
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uint8_t opcode = (instr & 0x01e00000) >> 21; |
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uint8_t opcode = (instr & 0x01E00000) >> 21; |
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bool S = (instr & 0x00100000) ? true : false; |
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if((instr & 0xfc000000) != 0xe0000000) { |
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if ((instr & 0xFC000000) != 0xE0000000) { |
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return false; |
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} else |
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if(!S && opcode >= 8 && opcode <= 11) { |
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} |
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else if (!S && opcode >= 8 && opcode <= 11) { |
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/* TST, TEQ, CMP and CMN all require S to be set */ |
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return false; |
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} else { |
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return true; |
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} |
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else |
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return true; |
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} |
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UnwResult UnwStartArm(UnwState * const state) { |
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@ -78,8 +78,8 @@ UnwResult UnwStartArm(UnwState * const state) { |
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* This is tested prior to data processing to prevent |
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* mis-interpretation as an invalid TEQ instruction. |
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*/ |
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if((instr & 0xfffffff0) == 0xe12fff10) { |
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uint8_t rn = instr & 0xf; |
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if ((instr & 0xFFFFFFF0) == 0xE12FFF10) { |
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uint8_t rn = instr & 0xF; |
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UnwPrintd4("BX r%d\t ; r%d %s\n", rn, rn, M_Origin2Str(state->regData[rn].o)); |
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@ -98,10 +98,9 @@ UnwResult UnwStartArm(UnwState * const state) { |
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UnwPrintd2(" Return PC=%x\n", state->regData[15].v & (~0x1)); |
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/* Report the return address */ |
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if(!UnwReportRetAddr(state, state->regData[rn].v)) { |
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if (!UnwReportRetAddr(state, state->regData[rn].v)) |
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return UNWIND_TRUNCATED; |
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} |
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} |
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/* Determine the return mode */ |
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if (state->regData[rn].v & 0x1) { |
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@ -118,16 +117,16 @@ UnwResult UnwStartArm(UnwState * const state) { |
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} |
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} |
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/* Branch */ |
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else if((instr & 0xff000000) == 0xea000000) { |
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else if ((instr & 0xFF000000) == 0xEA000000) { |
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int32_t offset = (instr & 0x00ffffff); |
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int32_t offset = (instr & 0x00FFFFFF); |
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/* Shift value */ |
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offset = offset << 2; |
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/* Sign extend if needed */ |
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if (offset & 0x02000000) { |
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offset |= 0xfc000000; |
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offset |= 0xFC000000; |
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} |
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UnwPrintd2("B %d\n", offset); |
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@ -142,11 +141,11 @@ UnwResult UnwStartArm(UnwState * const state) { |
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} |
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/* MRS */ |
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else if((instr & 0xffbf0fff) == 0xe10f0000) { |
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else if ((instr & 0xFFBF0FFF) == 0xE10F0000) { |
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#if defined(UNW_DEBUG) |
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bool R = (instr & 0x00400000) ? true : false; |
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#endif |
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uint8_t rd = (instr & 0x0000f000) >> 12; |
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uint8_t rd = (instr & 0x0000F000) >> 12; |
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UnwPrintd4("MRS r%d,%s\t; r%d invalidated", rd, R ? "SPSR" : "CPSR", rd); |
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@ -154,7 +153,7 @@ UnwResult UnwStartArm(UnwState * const state) { |
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state->regData[rd].o = REG_VAL_INVALID; |
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} |
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/* MSR */ |
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else if((instr & 0xffb0f000) == 0xe120f000) { |
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else if ((instr & 0xFFB0F000) == 0xE120F000) { |
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#if defined(UNW_DEBUG) |
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bool R = (instr & 0x00400000) ? true : false; |
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@ -172,13 +171,13 @@ UnwResult UnwStartArm(UnwState * const state) { |
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/* Data processing */ |
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else if (isDataProc(instr)) { |
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bool I = (instr & 0x02000000) ? true : false; |
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uint8_t opcode = (instr & 0x01e00000) >> 21; |
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uint8_t opcode = (instr & 0x01E00000) >> 21; |
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#if defined(UNW_DEBUG) |
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bool S = (instr & 0x00100000) ? true : false; |
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#endif |
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uint8_t rn = (instr & 0x000f0000) >> 16; |
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uint8_t rd = (instr & 0x0000f000) >> 12; |
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uint16_t operand2 = (instr & 0x00000fff); |
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uint8_t rn = (instr & 0x000F0000) >> 16; |
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uint8_t rd = (instr & 0x0000F000) >> 12; |
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uint16_t operand2 = (instr & 0x00000FFF); |
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uint32_t op2val; |
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int op2origin; |
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@ -203,8 +202,8 @@ UnwResult UnwStartArm(UnwState * const state) { |
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/* Decode operand 2 */ |
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if (I) { |
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uint8_t shiftDist = (operand2 & 0x0f00) >> 8; |
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uint8_t shiftConst = (operand2 & 0x00ff); |
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uint8_t shiftDist = (operand2 & 0x0F00) >> 8; |
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uint8_t shiftConst = (operand2 & 0x00FF); |
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/* rotate const right by 2 * shiftDist */ |
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shiftDist *= 2; |
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@ -217,7 +216,7 @@ UnwResult UnwStartArm(UnwState * const state) { |
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else { |
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/* Register and shift */ |
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uint8_t rm = (operand2 & 0x000f); |
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uint8_t rm = (operand2 & 0x000F); |
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uint8_t regShift = (operand2 & 0x0010) ? true : false; |
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uint8_t shiftType = (operand2 & 0x0060) >> 5; |
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uint32_t shiftDist; |
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@ -229,7 +228,7 @@ UnwResult UnwStartArm(UnwState * const state) { |
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/* Get the shift distance */ |
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if (regShift) { |
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uint8_t rs = (operand2 & 0x0f00) >> 8; |
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uint8_t rs = (operand2 & 0x0F00) >> 8; |
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if (operand2 & 0x00800) { |
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@ -249,7 +248,7 @@ UnwResult UnwStartArm(UnwState * const state) { |
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UnwPrintd7("%s r%d\t; r%d %s r%d %s", shiftMnu[shiftType], rs, rm, M_Origin2Str(state->regData[rm].o), rs, M_Origin2Str(state->regData[rs].o)); |
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} |
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else { |
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shiftDist = (operand2 & 0x0f80) >> 7; |
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shiftDist = (operand2 & 0x0F80) >> 7; |
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op2origin = REG_VAL_FROM_CONST; |
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if (shiftDist) { |
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@ -281,11 +280,11 @@ UnwResult UnwStartArm(UnwState * const state) { |
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/* Register shifts maybe greater than 32 */ |
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if (shiftDist >= 32) { |
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op2val = 0xffffffff; |
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op2val = 0xFFFFFFFF; |
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} |
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else { |
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op2val = state->regData[rm].v >> shiftDist; |
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op2val |= 0xffffffff << (32 - shiftDist); |
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op2val |= 0xFFFFFFFF << (32 - shiftDist); |
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} |
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} |
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else { |
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@ -305,7 +304,7 @@ UnwResult UnwStartArm(UnwState * const state) { |
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} |
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else { |
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/* Limit shift distance to 0-31 incase of register shift */ |
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shiftDist &= 0x1f; |
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shiftDist &= 0x1F; |
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op2val = (state->regData[rm].v >> shiftDist) | |
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(state->regData[rm].v << (32 - shiftDist)); |
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@ -441,15 +440,15 @@ UnwResult UnwStartArm(UnwState * const state) { |
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/* Block Data Transfer
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* LDM, STM |
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*/ |
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else if((instr & 0xfe000000) == 0xe8000000) { |
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else if ((instr & 0xFE000000) == 0xE8000000) { |
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bool P = (instr & 0x01000000) ? true : false; |
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bool U = (instr & 0x00800000) ? true : false; |
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bool S = (instr & 0x00400000) ? true : false; |
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bool W = (instr & 0x00200000) ? true : false; |
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bool L = (instr & 0x00100000) ? true : false; |
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uint16_t baseReg = (instr & 0x000f0000) >> 16; |
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uint16_t regList = (instr & 0x0000ffff); |
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uint16_t baseReg = (instr & 0x000F0000) >> 16; |
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uint16_t regList = (instr & 0x0000FFFF); |
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uint32_t addr = state->regData[baseReg].v; |
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bool addrValid = M_IsOriginValid(state->regData[baseReg].o); |
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int8_t r; |
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