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@ -231,33 +231,33 @@ |
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#if ENABLED(FYSETC_MINI_12864) |
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/**
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* The Fysetc display can NOT use the SCK and MOSI pins on EXP2, so a |
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* The FYSETC display can NOT use the SCK and MOSI pins on EXP2, so a |
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* special cable is needed to go between EXP2 on the FYSETC and the |
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* controller board's EXP2 and J8. It also means that a software SPI |
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* is needed to drive those pins. |
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* |
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* The Fysetc requires mode 3 SPI interface. |
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* The FYSETC requires mode 3 SPI interface. |
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* |
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* Pins 6, 7 & 8 on EXP2 are no connects. That means a second special |
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* cable will be needed if the RGB LEDs are to be active. |
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*/ |
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#define DOGLCD_CS LCD_PINS_ENABLE // EXP1.3 (LCD_EN on Fysetc schematic)
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#define DOGLCD_A0 LCD_PINS_RS // EXP1.4 (LCD_A0 on Fysetc schematic)
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#define DOGLCD_SCK P2_11 // J8-5 (SCK on Fysetc schematic)
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#define DOGLCD_MOSI P4_28 // J8-6 (MOSI on Fysetc schematic)
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#define DOGLCD_CS LCD_PINS_ENABLE // EXP1.3 (LCD_EN on FYSETC schematic)
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#define DOGLCD_A0 LCD_PINS_RS // EXP1.4 (LCD_A0 on FYSETC schematic)
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#define DOGLCD_SCK P2_11 // J8-5 (SCK on FYSETC schematic)
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#define DOGLCD_MOSI P4_28 // J8-6 (MOSI on FYSETC schematic)
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//#define FORCE_SOFT_SPI // Use this if default of hardware SPI causes display problems
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// results in LCD soft SPI mode 3, SD soft SPI mode 0
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#if EITHER(FYSETC_MINI_12864_1_2, FYSETC_MINI_12864_2_0) |
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#ifndef RGB_LED_R_PIN |
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#define RGB_LED_R_PIN P2_12 // J8-4 (LCD_D6 on Fysetc schematic)
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#define RGB_LED_R_PIN P2_12 // J8-4 (LCD_D6 on FYSETC schematic)
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#endif |
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#ifndef RGB_LED_G_PIN |
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#define RGB_LED_G_PIN P1_23 // J8-3 (LCD_D5 on Fysetc schematic)
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#define RGB_LED_G_PIN P1_23 // J8-3 (LCD_D5 on FYSETC schematic)
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#endif |
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#ifndef RGB_LED_B_PIN |
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#define RGB_LED_B_PIN P1_22 // J8-2 (LCD_D7 on Fysetc schematic)
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#define RGB_LED_B_PIN P1_22 // J8-2 (LCD_D7 on FYSETC schematic)
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#endif |
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#elif ENABLED(FYSETC_MINI_12864_2_1) |
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#define NEOPIXEL_PIN P2_12 |
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