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383 lines
15 KiB
383 lines
15 KiB
7 years ago
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/**
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* Marlin 3D Printer Firmware
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* Copyright (C) 2017 MarlinFirmware [https://github.com/MarlinFirmware/Marlin]
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*
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* Based on Sprinter and grbl.
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* Copyright (C) 2011 Camiel Gubbels / Erik van der Zalm
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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*/
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/**
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* The class Servo uses the PWM class to implement it's functions
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*
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* The PWM1 module is only used to generate interrups at specified times. It
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* is NOT used to directly toggle pins. The ISR writes to the pin assigned to
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* that interrupt
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*
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* All PWMs use the same repetition rate - 20mS because that's the normal servo rate
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*
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*/
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/**
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* The data structures are setup to minimize the computation done by the ISR which
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* minimizes ISR execution time. Execution times are 1.7 to 1.9 microseconds.
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*
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* Two tables are used. active_table is used by the ISR. Changes to the table are
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* are done by copying the active_table into the work_table, updating the work_table
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* and then swapping the two tables. Swapping is done by manipulating pointers.
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*
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* Immediately after the swap the ISR uses the work_table until the start of the
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* next 20mS cycle. During this transition the "work_table" is actually the table
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* that was being used before the swap. The "active_table" contains the data that
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* will start being used at the start of the next 20mS period. This keeps the pins
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* well behaved during the transition.
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*
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* The ISR's priority is set to the maximum otherwise other ISRs can cause considerable
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* jitter in the PWM high time.
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*/
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#ifdef TARGET_LPC1768
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#include <lpc17xx_pinsel.h>
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//#include "../HAL.h"
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//#include "../../../macros.h"
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#include "serial.h"
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typedef struct { // holds all data needed to control the 6 PWM channels
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uint8_t sequence; // 0: available slot, 1 - 6: PWM channel assigned to that slot
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uint8_t logical_pin;
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uint16_t PWM_mask;
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volatile uint32_t* set_register;
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volatile uint32_t* clr_register;
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uint32_t write_mask;
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uint32_t microseconds;
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uint32_t min;
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uint32_t max;
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bool PWM_flag; //
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uint8_t servo_index; // 0 - MAX_SERVO -1 : servo index, 0xFF : PWM channel
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bool active_flag;
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} PWM_map;
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#define MICRO_MAX 0xffffffff
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#define PWM_MAP_INIT_ROW {0, 0xff, 0, 0, 0, 0, MICRO_MAX, 0, 0, 0, 0, 0}
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#define PWM_MAP_INIT {PWM_MAP_INIT_ROW,\
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PWM_MAP_INIT_ROW,\
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PWM_MAP_INIT_ROW,\
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PWM_MAP_INIT_ROW,\
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PWM_MAP_INIT_ROW,\
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PWM_MAP_INIT_ROW,\
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};
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PWM_map PWM1_map_A[6] = PWM_MAP_INIT;
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PWM_map PWM1_map_B[6] = PWM_MAP_INIT;
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PWM_map *active_table = PWM1_map_A;
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PWM_map *work_table = PWM1_map_B;
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PWM_map *ISR_table;
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#define NUM_PWMS 6
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volatile uint8_t PWM1_ISR_index = 0;
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#define IR_BIT(p) (p >= 0 && p <= 3 ? p : p + 4 )
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#define COPY_ACTIVE_TABLE for (uint8_t i = 0; i < 6 ; i++) work_table[i] = active_table[i]
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#define PIN_IS_INVERTED(p) 0 // place holder in case inverting PWM output is offered
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/**
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* Prescale register and MR0 register values
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*
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* 100MHz PCLK 50MHz PCLK 25MHz PCLK 12.5MHz PCLK
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* ----------------- ----------------- ----------------- -----------------
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* desired prescale MR0 prescale MR0 prescale MR0 prescale MR0 resolution
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* prescale register register register register register register register register in degrees
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* freq value value value value value value value value
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*
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* 8 11.5 159,999 5.25 159,999 2.13 159,999 0.5625 159,999 0.023
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* 4 24 79,999 11.5 79,999 5.25 79,999 2.125 79,999 0.045
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* 2 49 39,999 24 39,999 11.5 39,999 5.25 39,999 0.090
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* 1 99 19,999 49 19,999 24 19,999 11.5 19,999 0.180
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* 0.5 199 9,999 99 9,999 49 9,999 24 9,999 0.360
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* 0.25 399 4,999 199 4,999 99 4,999 49 4,999 0.720
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* 0.125 799 2,499 399 2,499 199 2,499 99 2,499 1.440
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*
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* The desired prescale frequency comes from an input in the range of 544 - 2400 microseconds and the
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* desire to just shift the input left or right as needed.
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*
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* A resolution of 0.2 degrees seems reasonable so a prescale frequency output of 1MHz is being used.
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* It also means we don't need to scale the input.
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*
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* The PCLK is set to 25MHz because that's the slowest one that gives whole numbers for prescale and
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* MR0 registers.
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*
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* Final settings:
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* PCLKSEL0: 0x0
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* PWM1PR: 0x018 (24)
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* PWM1MR0: 0x04E1F (19,999)
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*
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*/
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#define LPC_PWM1_MR0 19999 // base repetition rate minus one count - 20mS
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#define LPC_PWM1_PR 24 // prescaler value - prescaler divide by 24 + 1 - 1 MHz output
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#define LPC_PWM1_PCLKSEL0 0x00 // select clock source for prescaler - defaults to 25MHz on power up
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// 0: 25MHz, 1: 100MHz, 2: 50MHz, 3: 12.5MHZ to PWM1 prescaler
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#define MR0_MARGIN 200 // if channel value too close to MR0 the system locks up
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void LPC1768_PWM_init(void) {
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#define SBIT_CNTEN 0 // PWM1 counter & pre-scaler enable/disable
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#define SBIT_CNTRST 1 // reset counters to known state
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#define SBIT_PWMEN 3 // 1 - PWM, 0 - timer
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#define SBIT_PWMMR0R 1
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#define PCPWM1 6
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#define PCLK_PWM1 12
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LPC_SC->PCONP |= (1 << PCPWM1); // enable PWM1 controller (enabled on power up)
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LPC_SC->PCLKSEL0 &= ~(0x3 << PCLK_PWM1);
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LPC_SC->PCLKSEL0 |= (LPC_PWM1_PCLKSEL0 << PCLK_PWM1);
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LPC_PWM1->MR0 = LPC_PWM1_MR0; // TC resets every 19,999 + 1 cycles - sets PWM cycle(Ton+Toff) to 20 mS
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// MR0 must be set before TCR enables the PWM
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LPC_PWM1->TCR = _BV(SBIT_CNTEN) | _BV(SBIT_CNTRST)| _BV(SBIT_PWMEN);; // enable counters, reset counters, set mode to PWM
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LPC_PWM1->TCR &= ~(_BV(SBIT_CNTRST)); // take counters out of reset
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LPC_PWM1->PR = LPC_PWM1_PR;
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LPC_PWM1->MCR = (_BV(SBIT_PWMMR0R) | _BV(0)); // Reset TC if it matches MR0, disable all interrupts except for MR0
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LPC_PWM1->CTCR = 0; // disable counter mode (enable PWM mode)
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LPC_PWM1->LER = 0x07F; // Set the latch Enable Bits to load the new Match Values for MR0 - MR6
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// Set all PWMs to single edge
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LPC_PWM1->PCR = 0; // single edge mode for all channels, PWM1 control of outputs off
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NVIC_EnableIRQ(PWM1_IRQn); // Enable interrupt handler
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// NVIC_SetPriority(PWM1_IRQn, NVIC_EncodePriority(0, 10, 0)); // normal priority for PWM module
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NVIC_SetPriority(PWM1_IRQn, NVIC_EncodePriority(0, 0, 0)); // minimizes jitter due to higher priority ISRs
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}
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bool PWM_table_swap; // flag to tell the ISR that the tables have been swapped
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bool LPC1768_PWM_attach_pin(uint8_t pin, uint32_t min = 1, uint32_t max = (LPC_PWM1_MR0 - MR0_MARGIN), uint8_t servo_index = 0xff) {
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COPY_ACTIVE_TABLE; // copy active table into work table
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uint8_t slot = 0;
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for (uint8_t i = 0; i < NUM_PWMS ; i++) // see if already in table
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if (work_table[i].logical_pin == pin) return 1;
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for (uint8_t i = 1; (i < NUM_PWMS + 1) && !slot; i++) // find empty slot
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if ( !(work_table[i - 1].set_register)) slot = i; // any item that can't be zero when active or just attached is OK
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if (!slot) return 0;
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slot--; // turn it into array index
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work_table[slot].logical_pin = pin; // init slot
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work_table[slot].PWM_mask = 0; // real value set by PWM_write
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work_table[slot].set_register = PIN_IS_INVERTED(pin) ? &LPC_GPIO(pin_map[pin].port)->FIOCLR : &LPC_GPIO(pin_map[pin].port)->FIOSET;
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work_table[slot].clr_register = PIN_IS_INVERTED(pin) ? &LPC_GPIO(pin_map[pin].port)->FIOSET : &LPC_GPIO(pin_map[pin].port)->FIOCLR;
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work_table[slot].write_mask = LPC_PIN(pin_map[pin].pin);
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work_table[slot].microseconds = MICRO_MAX;
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work_table[slot].min = min;
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work_table[slot].max = MIN(max, LPC_PWM1_MR0 - MR0_MARGIN);
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work_table[slot].servo_index = servo_index;
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work_table[slot].active_flag = false;
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//swap tables
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NVIC_DisableIRQ(PWM1_IRQn);
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PWM_map *pointer_swap = active_table;
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active_table = work_table;
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work_table = pointer_swap;
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PWM_table_swap = true; // tell the ISR that the tables have been swapped
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NVIC_EnableIRQ(PWM1_IRQn); // re-enable PWM interrupts
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return 1;
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}
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bool LPC1768_PWM_write(uint8_t pin, uint32_t value) {
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COPY_ACTIVE_TABLE; // copy active table into work table
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uint8_t slot = 0xFF;
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for (uint8_t i = 0; i < NUM_PWMS; i++) // find slot
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if (work_table[i].logical_pin == pin) slot = i;
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if (slot == 0xFF) return false; // return error if pin not found
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digitalWrite(pin, 0); // set pin to output & set it low
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work_table[slot].microseconds = MAX(MIN(value, work_table[slot].max), work_table[slot].min);
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work_table[slot].active_flag = true;
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for (uint8_t i = NUM_PWMS; --i;) { // (bubble) sort table by microseconds
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bool didSwap = false;
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PWM_map temp;
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for (uint16_t j = 0; j < i; ++j) {
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if (work_table[j].microseconds > work_table[j + 1].microseconds) {
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temp = work_table[j + 1];
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work_table[j + 1] = work_table[j];
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work_table[j] = temp;
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didSwap = true;
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}
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}
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if (!didSwap) break;
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}
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for (uint8_t i = 0; i < NUM_PWMS; i++) // set the index & PWM_mask
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if (work_table[i].active_flag == true) {
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work_table[i].sequence = i + 1;
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work_table[i].PWM_mask = _BV(IR_BIT(i + 1));
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}
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else work_table[i].sequence = 0;
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uint32_t interrupt_mask = 0; // set match registers to new values, build IRQ mask
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if (work_table[0].active_flag == true) {
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LPC_PWM1->MR1 = work_table[0].microseconds;
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interrupt_mask |= _BV(3);
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}
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if (work_table[1].active_flag == true) {
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LPC_PWM1->MR2 = work_table[1].microseconds;
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interrupt_mask |= _BV(6);
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}
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if (work_table[2].active_flag == true) {
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LPC_PWM1->MR3 = work_table[2].microseconds;
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interrupt_mask |= _BV(9);
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}
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if (work_table[3].active_flag == true) {
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LPC_PWM1->MR4 = work_table[3].microseconds;
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interrupt_mask |= _BV(12);
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}
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if (work_table[4].active_flag == true) {
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LPC_PWM1->MR5 = work_table[4].microseconds;
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interrupt_mask |= _BV(15);
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}
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if (work_table[5].active_flag == true) {
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LPC_PWM1->MR6 = work_table[5].microseconds;
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interrupt_mask |= _BV(18);
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}
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interrupt_mask |= _BV(0); // add in MR0 interrupt
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// swap tables
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NVIC_DisableIRQ(PWM1_IRQn);
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LPC_PWM1->LER = 0x07E; // Set the latch Enable Bits to load the new Match Values for MR1 - MR6
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PWM_map *pointer_swap = active_table;
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active_table = work_table;
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work_table = pointer_swap;
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PWM_table_swap = true; // tell the ISR that the tables have been swapped
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LPC_PWM1->MCR = interrupt_mask; // enable new PWM individual channel interrupts
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NVIC_EnableIRQ(PWM1_IRQn); // re-enable PWM interrupts
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return 1;
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}
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bool LPC1768_PWM_detach_pin(uint8_t pin) {
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COPY_ACTIVE_TABLE; // copy active table into work table
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uint8_t slot = 0xFF;
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for (uint8_t i = 0; i < NUM_PWMS; i++) // find slot
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if (work_table[i].logical_pin == pin) slot = i;
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if (slot == 0xFF) return false; // return error if pin not found
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pinMode(pin, INPUT_PULLUP); // set pin to input with pullup
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work_table[slot] = PWM_MAP_INIT_ROW;
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for (uint8_t i = NUM_PWMS; --i;) { // (bubble) sort table by microseconds
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bool didSwap = false;
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PWM_map temp;
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for (uint16_t j = 0; j < i; ++j) {
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if (work_table[j].microseconds > work_table[j + 1].microseconds) {
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temp = work_table[j + 1];
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work_table[j + 1] = work_table[j];
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work_table[j] = temp;
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didSwap = true;
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}
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}
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if (!didSwap) break;
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}
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for (uint8_t i = 0; i < NUM_PWMS; i++) // set the index & PWM_mask
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if (work_table[i].active_flag == true) {
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work_table[i].sequence = i + 1;
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work_table[i].PWM_mask = _BV(IR_BIT(i + 1));
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}
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else work_table[i].sequence = 0;
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||
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|
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||
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uint32_t interrupt_mask = 0; // set match registers to new values, build IRQ mask
|
||
|
|
if (work_table[0].active_flag == true) {
|
||
|
|
LPC_PWM1->MR1 = work_table[0].microseconds;
|
||
|
|
interrupt_mask |= _BV(3);
|
||
|
|
}
|
||
|
|
if (work_table[1].active_flag == true) {
|
||
|
|
LPC_PWM1->MR2 = work_table[1].microseconds;
|
||
|
|
interrupt_mask |= _BV(6);
|
||
|
|
}
|
||
|
|
if (work_table[2].active_flag == true) {
|
||
|
|
LPC_PWM1->MR3 = work_table[2].microseconds;
|
||
|
|
interrupt_mask |= _BV(9);
|
||
|
|
}
|
||
|
|
if (work_table[3].active_flag == true) {
|
||
|
|
LPC_PWM1->MR4 = work_table[3].microseconds;
|
||
|
|
interrupt_mask |= _BV(12);
|
||
|
|
}
|
||
|
|
if (work_table[4].active_flag == true) {
|
||
|
|
LPC_PWM1->MR5 = work_table[4].microseconds;
|
||
|
|
interrupt_mask |= _BV(15);
|
||
|
|
}
|
||
|
|
if (work_table[5].active_flag == true) {
|
||
|
|
LPC_PWM1->MR6 = work_table[5].microseconds;
|
||
|
|
interrupt_mask |= _BV(18);
|
||
|
|
}
|
||
|
|
|
||
|
|
interrupt_mask |= _BV(0); // add in MR0 interrupt
|
||
|
|
|
||
|
|
// swap tables
|
||
|
|
NVIC_DisableIRQ(PWM1_IRQn);
|
||
|
|
LPC_PWM1->LER = 0x07E; // Set the latch Enable Bits to load the new Match Values for MR1 - MR6
|
||
|
|
PWM_map *pointer_swap = active_table;
|
||
|
|
active_table = work_table;
|
||
|
|
work_table = pointer_swap;
|
||
|
|
PWM_table_swap = true; // tell the ISR that the tables have been swapped
|
||
|
|
LPC_PWM1->MCR = interrupt_mask; // enable remaining PWM individual channel interrupts
|
||
|
|
NVIC_EnableIRQ(PWM1_IRQn); // re-enable PWM interrupts
|
||
|
|
|
||
|
|
return 1;
|
||
|
|
}
|
||
|
|
|
||
|
|
////////////////////////////////////////////////////////////////////////////////
|
||
|
|
|
||
|
|
#define HAL_PWM_LPC1768_ISR extern "C" void PWM1_IRQHandler(void)
|
||
|
|
|
||
|
|
HAL_PWM_LPC1768_ISR {
|
||
|
|
if (PWM_table_swap) ISR_table = work_table; // use old table if a swap was just done
|
||
|
|
else ISR_table = active_table;
|
||
|
|
|
||
|
|
if (LPC_PWM1->IR & 0x1) { // MR0 interrupt
|
||
|
|
PWM_table_swap = false; // MR0 means new values could have been
|
||
|
|
ISR_table = active_table; // loaded so set everything to normal operation
|
||
|
|
for (uint8_t i = 0; (i < NUM_PWMS) && ISR_table[i].active_flag ; i++)
|
||
|
|
*ISR_table[i].set_register = ISR_table[i].write_mask; // set all enabled channels active
|
||
|
|
LPC_PWM1->IR = 0x01; // clear the MR0 interrupt flag bit
|
||
|
|
PWM1_ISR_index = 0;
|
||
|
|
}
|
||
|
|
else {
|
||
|
|
if (ISR_table[PWM1_ISR_index].active_flag && (LPC_PWM1->IR & ISR_table[PWM1_ISR_index].PWM_mask)) {
|
||
|
|
LPC_PWM1->IR = ISR_table[PWM1_ISR_index].PWM_mask; // clear the interrupt flag bit
|
||
|
|
*ISR_table[PWM1_ISR_index].clr_register = ISR_table[PWM1_ISR_index].write_mask; // set channel to inactive
|
||
|
|
}
|
||
|
|
PWM1_ISR_index++; // should be the index for the next interrupt
|
||
|
|
}
|
||
|
|
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
|
||
|
|
#endif
|