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379 lines
17 KiB
379 lines
17 KiB
/**
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* Marlin 3D Printer Firmware
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* Copyright (c) 2021 MarlinFirmware [https://github.com/MarlinFirmware/Marlin]
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*
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* Based on Sprinter and grbl.
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* Copyright (c) 2011 Camiel Gubbels / Erik van der Zalm
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* Copyright (c) 2020 Cyril Russo
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <https://www.gnu.org/licenses/>.
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*
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*/
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/***************************************************************************
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* ARM CPU Exception handler
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***************************************************************************/
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#if defined(__arm__) || defined(__thumb__)
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/*
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On ARM CPUs exception handling is quite powerful.
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By default, upon a crash, the CPU enters the handlers that have a higher priority than any other interrupts,
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so, in effect, no (real) interrupt can "interrupt" the handler (it's acting like if interrupts were disabled).
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If the handler is not called as re-entrant (that is, if the crash is not happening inside an interrupt or an handler),
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then it'll patch the return address to a dumping function (resume_from_fault) and save the crash state.
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The CPU will exit the handler and, as such, re-allow the other interrupts, and jump to the dumping function.
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In this function, the usual serial port (USB / HW) will be used to dump the crash (no special configuration required).
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The only case where it requires hardware UART is when it's crashing in an interrupt or a crash handler.
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In that case, instead of returning to the resume_from_fault function (and thus, re-enabling interrupts),
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it jumps to this function directly (so with interrupts disabled), after changing the behavior of the serial output
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wrapper to use the HW uart (and in effect, calling MinSerial::init which triggers a warning if you are using
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a USB serial port).
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In the case you have a USB serial port, this part will be disabled, and only that part (so that's the reason for
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the warning).
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This means that you can't have a crash report if the crash happens in an interrupt or an handler if you are using
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a USB serial port since it's physically impossible.
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You will get a crash report in all other cases.
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*/
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#include "exception_hook.h"
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#include "../backtrace/backtrace.h"
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#include "../HAL_MinSerial.h"
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#define HW_REG(X) (*((volatile unsigned long *)(X)))
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// Default function use the CPU VTOR register to get the vector table.
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// Accessing the CPU VTOR register is done in assembly since it's the only way that's common to all current tool
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unsigned long get_vtor() { return HW_REG(0xE000ED08); } // Even if it looks like an error, it is not an error
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void * hook_get_hardfault_vector_address(unsigned vtor) { return (void*)(vtor + 0x03); }
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void * hook_get_memfault_vector_address(unsigned vtor) { return (void*)(vtor + 0x04); }
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void * hook_get_busfault_vector_address(unsigned vtor) { return (void*)(vtor + 0x05); }
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void * hook_get_usagefault_vector_address(unsigned vtor) { return (void*)(vtor + 0x06); }
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void * hook_get_reserved_vector_address(unsigned vtor) { return (void*)(vtor + 0x07); }
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// Common exception frame for ARM, should work for all ARM CPU
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// Described here (modified for convenience): https://interrupt.memfault.com/blog/cortex-m-fault-debug
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struct __attribute__((packed)) ContextStateFrame {
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uint32_t r0;
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uint32_t r1;
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uint32_t r2;
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uint32_t r3;
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uint32_t r12;
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uint32_t lr;
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uint32_t pc;
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uint32_t xpsr;
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};
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struct __attribute__((packed)) ContextSavedFrame {
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uint32_t R0;
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uint32_t R1;
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uint32_t R2;
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uint32_t R3;
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uint32_t R12;
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uint32_t LR;
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uint32_t PC;
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uint32_t XPSR;
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uint32_t CFSR;
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uint32_t HFSR;
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uint32_t DFSR;
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uint32_t AFSR;
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uint32_t MMAR;
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uint32_t BFAR;
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uint32_t ESP;
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uint32_t ELR;
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};
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#if NONE(STM32F0xx, STM32G0xx)
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extern "C"
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__attribute__((naked)) void CommonHandler_ASM() {
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__asm__ __volatile__ (
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// Bit 2 of LR tells which stack pointer to use (either main or process, only main should be used anyway)
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"tst lr, #4\n"
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"ite eq\n"
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"mrseq r0, msp\n"
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"mrsne r0, psp\n"
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// Save the LR in use when being interrupted
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"mov r1, lr\n"
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// Get the exception number from the ICSR register
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"ldr r2, =0xE000ED00\n"
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"ldr r2, [r2, #4]\n"
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"b CommonHandler_C\n"
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);
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}
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#else // Cortex M0 does not support conditional mov and testing with a constant, so let's have a specific handler for it
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extern "C"
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__attribute__((naked)) void CommonHandler_ASM() {
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__asm__ __volatile__ (
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".syntax unified\n"
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// Save the LR in use when being interrupted
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"mov r1, lr\n"
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// Get the exception number from the ICSR register
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"ldr r2, =0xE000ED00\n"
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"ldr r2, [r2, #4]\n"
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"movs r0, #4\n"
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"tst r1, r0\n"
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"beq _MSP\n"
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"mrs r0, psp\n"
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"b CommonHandler_C\n"
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"_MSP:\n"
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"mrs r0, msp\n"
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"b CommonHandler_C\n"
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);
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}
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#if DISABLED(DYNAMIC_VECTORTABLE) // Cortex M0 requires the handler's address to be within 32kB to the actual function to be able to branch to it
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extern "C" {
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void __attribute__((naked, alias("CommonHandler_ASM"), nothrow)) __exc_hardfault();
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void __attribute__((naked, alias("CommonHandler_ASM"), nothrow)) __exc_busfault();
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void __attribute__((naked, alias("CommonHandler_ASM"), nothrow)) __exc_usagefault();
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void __attribute__((naked, alias("CommonHandler_ASM"), nothrow)) __exc_memmanage();
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void __attribute__((naked, alias("CommonHandler_ASM"), nothrow)) __exc_nmi();
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void __attribute__((naked, alias("CommonHandler_ASM"), nothrow)) __stm32reservedexception7();
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void __attribute__((naked, alias("CommonHandler_ASM"), nothrow)) __stm32reservedexception8();
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void __attribute__((naked, alias("CommonHandler_ASM"), nothrow)) __stm32reservedexception9();
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void __attribute__((naked, alias("CommonHandler_ASM"), nothrow)) __stm32reservedexception10();
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void __attribute__((naked, alias("CommonHandler_ASM"), nothrow)) __stm32reservedexception13();
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}
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//TODO When going off from libmaple, you'll need to replace those by the one from STM32/HAL_MinSerial.cpp
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#endif
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#endif
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// Must be a macro to avoid creating a function frame
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#define HALT_IF_DEBUGGING() \
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do { \
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if (HW_REG(0xE000EDF0) & _BV(0)) { \
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__asm("bkpt 1"); \
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} \
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} while (0)
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// Resume from a fault (if possible) so we can still use interrupt based code for serial output
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// In that case, we will not jump back to the faulty code, but instead to a dumping code and then a
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// basic loop with watchdog calling or manual resetting
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static ContextSavedFrame savedFrame;
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static uint8_t lastCause;
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bool resume_from_fault() {
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static const char* causestr[] = { "Thread", "Rsvd", "NMI", "Hard", "Mem", "Bus", "Usage", "7", "8", "9", "10", "SVC", "Dbg", "13", "PendSV", "SysTk", "IRQ" };
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// Reinit the serial link (might only work if implemented in each of your boards)
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MinSerial::init();
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MinSerial::TX("\n\n## Software Fault detected ##\n");
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MinSerial::TX("Cause: "); MinSerial::TX(causestr[min(lastCause, (uint8_t)16)]); MinSerial::TX('\n');
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MinSerial::TX("R0 : "); MinSerial::TXHex(savedFrame.R0); MinSerial::TX('\n');
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MinSerial::TX("R1 : "); MinSerial::TXHex(savedFrame.R1); MinSerial::TX('\n');
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MinSerial::TX("R2 : "); MinSerial::TXHex(savedFrame.R2); MinSerial::TX('\n');
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MinSerial::TX("R3 : "); MinSerial::TXHex(savedFrame.R3); MinSerial::TX('\n');
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MinSerial::TX("R12 : "); MinSerial::TXHex(savedFrame.R12); MinSerial::TX('\n');
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MinSerial::TX("LR : "); MinSerial::TXHex(savedFrame.LR); MinSerial::TX('\n');
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MinSerial::TX("PC : "); MinSerial::TXHex(savedFrame.PC); MinSerial::TX('\n');
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MinSerial::TX("PSR : "); MinSerial::TXHex(savedFrame.XPSR); MinSerial::TX('\n');
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// Configurable Fault Status Register
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// Consists of MMSR, BFSR and UFSR
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MinSerial::TX("CFSR : "); MinSerial::TXHex(savedFrame.CFSR); MinSerial::TX('\n');
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// Hard Fault Status Register
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MinSerial::TX("HFSR : "); MinSerial::TXHex(savedFrame.HFSR); MinSerial::TX('\n');
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// Debug Fault Status Register
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MinSerial::TX("DFSR : "); MinSerial::TXHex(savedFrame.DFSR); MinSerial::TX('\n');
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// Auxiliary Fault Status Register
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MinSerial::TX("AFSR : "); MinSerial::TXHex(savedFrame.AFSR); MinSerial::TX('\n');
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// Read the Fault Address Registers. These may not contain valid values.
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// Check BFARVALID/MMARVALID to see if they are valid values
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// MemManage Fault Address Register
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MinSerial::TX("MMAR : "); MinSerial::TXHex(savedFrame.MMAR); MinSerial::TX('\n');
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// Bus Fault Address Register
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MinSerial::TX("BFAR : "); MinSerial::TXHex(savedFrame.BFAR); MinSerial::TX('\n');
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MinSerial::TX("ExcLR: "); MinSerial::TXHex(savedFrame.ELR); MinSerial::TX('\n');
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MinSerial::TX("ExcSP: "); MinSerial::TXHex(savedFrame.ESP); MinSerial::TX('\n');
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// The stack pointer is pushed by 8 words upon entering an exception, so we need to revert this
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backtrace_ex(savedFrame.ESP + 8*4, savedFrame.LR, savedFrame.PC);
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// Call the last resort function here
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hook_last_resort_func();
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const uint32_t start = millis(), end = start + 100; // 100ms should be enough
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// We need to wait for the serial buffers to be output but we don't know for how long
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// So we'll just need to refresh the watchdog for a while and then stop for the system to reboot
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uint32_t last = start;
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while (PENDING(last, end)) {
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watchdog_refresh();
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while (millis() == last) { /* nada */ }
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last = millis();
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MinSerial::TX('.');
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}
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// Reset now by reinstantiating the bootloader's vector table
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HW_REG(0xE000ED08) = 0;
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// Restart watchdog
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#if DISABLED(USE_WATCHDOG)
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// No watchdog, let's perform ARMv7 reset instead by writing to AIRCR register with VECTKEY set to SYSRESETREQ
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HW_REG(0xE000ED0C) = (HW_REG(0xE000ED0C) & 0x0000FFFF) | 0x05FA0004;
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#endif
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while(1) {} // Bad luck, nothing worked
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}
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// Make sure the compiler does not optimize the frame argument away
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extern "C"
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__attribute__((optimize("O0")))
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void CommonHandler_C(ContextStateFrame * frame, unsigned long lr, unsigned long cause) {
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// If you are using it'll stop here
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HALT_IF_DEBUGGING();
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// Save the state to backtrace later on (don't call memcpy here since the stack can be corrupted)
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savedFrame.R0 = frame->r0;
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savedFrame.R1 = frame->r1;
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savedFrame.R2 = frame->r2;
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savedFrame.R3 = frame->r3;
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savedFrame.R12 = frame->r12;
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savedFrame.LR = frame->lr;
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savedFrame.PC = frame->pc;
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savedFrame.XPSR= frame->xpsr;
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lastCause = cause & 0x1FF;
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volatile uint32_t &CFSR = HW_REG(0xE000ED28);
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savedFrame.CFSR = CFSR;
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savedFrame.HFSR = HW_REG(0xE000ED2C);
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savedFrame.DFSR = HW_REG(0xE000ED30);
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savedFrame.AFSR = HW_REG(0xE000ED3C);
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savedFrame.MMAR = HW_REG(0xE000ED34);
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savedFrame.BFAR = HW_REG(0xE000ED38);
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savedFrame.ESP = (unsigned long)frame; // Even on return, this should not be overwritten by the CPU
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savedFrame.ELR = lr;
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// First check if we can resume from this exception to our own handler safely
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// If we can, then we don't need to disable interrupts and the usual serial code
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// can be used
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//const uint32_t non_usage_fault_mask = 0x0000FFFF;
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//const bool non_usage_fault_occurred = (CFSR & non_usage_fault_mask) != 0;
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// the bottom 8 bits of the xpsr hold the exception number of the
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// executing exception or 0 if the processor is in Thread mode
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const bool faulted_from_exception = ((frame->xpsr & 0xFF) != 0);
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if (!faulted_from_exception) { // Not sure about the non_usage_fault, we want to try anyway, don't we ? && !non_usage_fault_occurred)
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// Try to resume to our handler here
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CFSR |= CFSR; // The ARM programmer manual says you must write to 1 all fault bits to clear them so this instruction is correct
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// The frame will not be valid when returning anymore, let's clean it
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savedFrame.CFSR = 0;
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frame->pc = (uint32_t)resume_from_fault; // Patch where to return to
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frame->lr = 0xDEADBEEF; // If our handler returns (it shouldn't), let's make it trigger an exception immediately
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frame->xpsr = _BV(24); // Need to clean the PSR register to thumb II only
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MinSerial::force_using_default_output = true;
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return; // The CPU will resume in our handler hopefully, and we'll try to use default serial output
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}
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// Sorry, we need to emergency code here since the fault is too dangerous to recover from
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MinSerial::force_using_default_output = false;
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resume_from_fault();
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}
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void hook_cpu_exceptions() {
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#if ENABLED(DYNAMIC_VECTORTABLE)
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// On ARM 32bits CPU, the vector table is like this:
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// 0x0C => Hardfault
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// 0x10 => MemFault
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// 0x14 => BusFault
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// 0x18 => UsageFault
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// Unfortunately, it's usually run from flash, and we can't write to flash here directly to hook our instruction
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// We could set an hardware breakpoint, and hook on the fly when it's being called, but this
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// is hard to get right and would probably break debugger when attached
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// So instead, we'll allocate a new vector table filled with the previous value except
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// for the fault we are interested in.
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// Now, comes the issue to figure out what is the current vector table size
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// There is nothing telling us what is the vector table as it's per-cpu vendor specific.
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// BUT: we are being called at the end of the setup, so we assume the setup is done
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// Thus, we can read the current vector table until we find an address that's not in flash, and it would mark the
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// end of the vector table (skipping the fist entry obviously)
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// The position of the program in flash is expected to be at 0x08xxx xxxx on all known platform for ARM and the
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// flash size is available via register 0x1FFFF7E0 on STM32 family, but it's not the case for all ARM boards
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// (accessing this register might trigger a fault if it's not implemented).
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// So we'll simply mask the top 8 bits of the first handler as an hint of being in the flash or not -that's poor and will
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// probably break if the flash happens to be more than 128MB, but in this case, we are not magician, we need help from outside.
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unsigned long *vecAddr = (unsigned long*)get_vtor();
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SERIAL_ECHOPGM("Vector table addr: ");
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SERIAL_PRINTLN(get_vtor(), PrintBase::Hex);
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#ifdef VECTOR_TABLE_SIZE
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uint32_t vec_size = VECTOR_TABLE_SIZE;
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alignas(128) static unsigned long vectable[VECTOR_TABLE_SIZE] ;
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#else
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#ifndef IS_IN_FLASH
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#define IS_IN_FLASH(X) (((unsigned long)X & 0xFF000000) == 0x08000000)
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#endif
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// When searching for the end of the vector table, this acts as a limit not to overcome
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#ifndef VECTOR_TABLE_SENTINEL
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#define VECTOR_TABLE_SENTINEL 80
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#endif
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// Find the vector table size
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uint32_t vec_size = 1;
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while (IS_IN_FLASH(vecAddr[vec_size]) && vec_size < VECTOR_TABLE_SENTINEL)
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vec_size++;
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// We failed to find a valid vector table size, let's abort hooking up
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if (vec_size == VECTOR_TABLE_SENTINEL) return;
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// Poor method that's wasting RAM here, but allocating with malloc and alignment would be worst
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// 128 bytes alignment is required for writing the VTOR register
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alignas(128) static unsigned long vectable[VECTOR_TABLE_SENTINEL];
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SERIAL_ECHOPGM("Detected vector table size: ");
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SERIAL_PRINTLN(vec_size, PrintBase::Hex);
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#endif
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uint32_t defaultFaultHandler = vecAddr[(unsigned)7];
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// Copy the current vector table into the new table
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for (uint32_t i = 0; i < vec_size; i++) {
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vectable[i] = vecAddr[i];
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// Replace all default handler by our own handler
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if (vectable[i] == defaultFaultHandler)
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vectable[i] = (unsigned long)&CommonHandler_ASM;
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}
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// Let's hook now with our functions
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vectable[(unsigned long)hook_get_hardfault_vector_address(0)] = (unsigned long)&CommonHandler_ASM;
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vectable[(unsigned long)hook_get_memfault_vector_address(0)] = (unsigned long)&CommonHandler_ASM;
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vectable[(unsigned long)hook_get_busfault_vector_address(0)] = (unsigned long)&CommonHandler_ASM;
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vectable[(unsigned long)hook_get_usagefault_vector_address(0)] = (unsigned long)&CommonHandler_ASM;
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// Finally swap with our own vector table
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// This is supposed to be atomic, but let's do that with interrupt disabled
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HW_REG(0xE000ED08) = (unsigned long)vectable | _BV32(29); // 29th bit is for telling the CPU the table is now in SRAM (should be present already)
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SERIAL_ECHOLNPGM("Installed fault handlers");
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#endif
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}
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#endif // __arm__ || __thumb__
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