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210 lines
6.5 KiB
210 lines
6.5 KiB
/***************************************************************************
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* ARM Stack Unwinder, Michael.McTernan.2001@cs.bris.ac.uk
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* Updated, adapted and several bug fixes on 2018 by Eduardo José Tagle
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*
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* This program is PUBLIC DOMAIN.
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* This means that there is no copyright and anyone is able to take a copy
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* for free and use it as they wish, with or without modifications, and in
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* any context, commercially or otherwise. The only limitation is that I
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* don't guarantee that the software is fit for any purpose or accept any
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* liability for its use or misuse - this software is without warranty.
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***************************************************************************
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* File Description: Utility functions to access memory
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**************************************************************************/
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#if defined(__arm__) || defined(__thumb__)
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#include "unwmemaccess.h"
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#include "../../../inc/MarlinConfig.h"
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/* Validate address */
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#ifdef ARDUINO_ARCH_SAM
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// For DUE, valid address ranges are
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// SRAM (0x20070000 - 0x20088000) (96kb)
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// FLASH (0x00080000 - 0x00100000) (512kb)
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//
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#define START_SRAM_ADDR 0x20070000
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#define END_SRAM_ADDR 0x20088000
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#define START_FLASH_ADDR 0x00080000
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#define END_FLASH_ADDR 0x00100000
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#elif defined(TARGET_LPC1768)
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// For LPC1769:
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// SRAM (0x10000000 - 0x10008000) (32kb)
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// FLASH (0x00000000 - 0x00080000) (512kb)
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//
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#define START_SRAM_ADDR 0x10000000
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#define END_SRAM_ADDR 0x10008000
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#define START_FLASH_ADDR 0x00000000
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#define END_FLASH_ADDR 0x00080000
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#elif defined(__STM32F1__) || defined(STM32F1xx) || defined(STM32F0xx) || defined(STM32G0xx)
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// For STM32F103ZET6/STM32F103VET6/STM32F0xx
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// SRAM (0x20000000 - 0x20010000) (64kb)
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// FLASH (0x08000000 - 0x08080000) (512kb)
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//
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#define START_SRAM_ADDR 0x20000000
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#define END_SRAM_ADDR 0x20010000
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#define START_FLASH_ADDR 0x08000000
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#define END_FLASH_ADDR 0x08080000
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#elif defined(STM32F4) || defined(STM32F4xx)
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// For STM32F407VET
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// SRAM (0x20000000 - 0x20030000) (192kb)
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// FLASH (0x08000000 - 0x08080000) (512kb)
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//
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#define START_SRAM_ADDR 0x20000000
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#define END_SRAM_ADDR 0x20030000
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#define START_FLASH_ADDR 0x08000000
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#define END_FLASH_ADDR 0x08080000
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#elif MB(REMRAM_V1, NUCLEO_F767ZI)
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// For STM32F765VI in RemRam v1
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// SRAM (0x20000000 - 0x20080000) (512kb)
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// FLASH (0x08000000 - 0x08200000) (2048kb)
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//
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#define START_SRAM_ADDR 0x20000000
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#define END_SRAM_ADDR 0x20080000
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#define START_FLASH_ADDR 0x08000000
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#define END_FLASH_ADDR 0x08200000
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#elif defined(__MK20DX256__)
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// For MK20DX256 in TEENSY 3.1 or TEENSY 3.2
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// SRAM (0x1FFF8000 - 0x20008000) (64kb)
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// FLASH (0x00000000 - 0x00040000) (256kb)
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//
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#define START_SRAM_ADDR 0x1FFF8000
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#define END_SRAM_ADDR 0x20008000
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#define START_FLASH_ADDR 0x00000000
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#define END_FLASH_ADDR 0x00040000
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#elif defined(__MK64FX512__)
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// For MK64FX512 in TEENSY 3.5
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// SRAM (0x1FFF0000 - 0x20020000) (192kb)
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// FLASH (0x00000000 - 0x00080000) (512kb)
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//
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#define START_SRAM_ADDR 0x1FFF0000
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#define END_SRAM_ADDR 0x20020000
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#define START_FLASH_ADDR 0x00000000
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#define END_FLASH_ADDR 0x00080000
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#elif defined(__MK66FX1M0__)
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// For MK66FX1M0 in TEENSY 3.6
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// SRAM (0x1FFF0000 - 0x20030000) (256kb)
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// FLASH (0x00000000 - 0x00140000) (1.25Mb)
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//
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#define START_SRAM_ADDR 0x1FFF0000
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#define END_SRAM_ADDR 0x20030000
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#define START_FLASH_ADDR 0x00000000
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#define END_FLASH_ADDR 0x00140000
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#elif defined(__IMXRT1062__)
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// For IMXRT1062 in TEENSY 4.0/4/1
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// ITCM (rwx): ORIGIN = 0x00000000, LENGTH = 512K
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// DTCM (rwx): ORIGIN = 0x20000000, LENGTH = 512K
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// RAM (rwx): ORIGIN = 0x20200000, LENGTH = 512K
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// FLASH (rwx): ORIGIN = 0x60000000, LENGTH = 1984K
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//
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#define START_SRAM_ADDR 0x00000000
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#define END_SRAM_ADDR 0x20280000
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#define START_FLASH_ADDR 0x60000000
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#define END_FLASH_ADDR 0x601F0000
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#elif defined(__SAMD51P20A__)
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// For SAMD51x20, valid address ranges are
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// SRAM (0x20000000 - 0x20040000) (256kb)
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// FLASH (0x00000000 - 0x00100000) (1024kb)
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//
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#define START_SRAM_ADDR 0x20000000
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#define END_SRAM_ADDR 0x20040000
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#define START_FLASH_ADDR 0x00000000
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#define END_FLASH_ADDR 0x00100000
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#else
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// Generic ARM code, that's testing if an access to the given address would cause a fault or not
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// It can't guarantee an address is in RAM or Flash only, but we usually don't care
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#define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status Reg.
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#define NVIC_CFG_CTRL 0xE000ED14 // Configuration Control Register
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#define NVIC_FAULT_STAT_BFARV 0x00008000 // BFAR is valid
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#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore bus fault in NMI/fault
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#define HW_REG(X) (*((volatile unsigned long *)(X)))
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static bool validate_addr(uint32_t read_address) {
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bool works = true;
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uint32_t intDisabled = 0;
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// Read current interrupt state
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__asm__ __volatile__ ("MRS %[result], PRIMASK\n\t" : [result]"=r"(intDisabled) :: ); // 0 is int enabled, 1 for disabled
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// Clear bus fault indicator first (write 1 to clear)
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HW_REG(NVIC_FAULT_STAT) |= NVIC_FAULT_STAT_BFARV;
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// Ignore bus fault interrupt
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HW_REG(NVIC_CFG_CTRL) |= NVIC_CFG_CTRL_BFHFNMIGN;
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// Disable interrupts if not disabled previously
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if (!intDisabled) __asm__ __volatile__ ("CPSID f");
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// Probe address
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*(volatile uint32_t*)read_address;
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// Check if a fault happened
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if ((HW_REG(NVIC_FAULT_STAT) & NVIC_FAULT_STAT_BFARV) != 0)
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works = false;
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// Enable interrupts again if previously disabled
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if (!intDisabled) __asm__ __volatile__ ("CPSIE f");
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// Enable fault interrupt flag
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HW_REG(NVIC_CFG_CTRL) &= ~NVIC_CFG_CTRL_BFHFNMIGN;
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return works;
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}
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#endif
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#ifdef START_SRAM_ADDR
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static bool validate_addr(uint32_t addr) {
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// Address must be in SRAM range
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if (addr >= START_SRAM_ADDR && addr < END_SRAM_ADDR)
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return true;
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// Or in FLASH range
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if (addr >= START_FLASH_ADDR && addr < END_FLASH_ADDR)
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return true;
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return false;
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}
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#endif
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bool UnwReadW(const uint32_t a, uint32_t *v) {
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if (!validate_addr(a))
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return false;
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*v = *(uint32_t *)a;
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return true;
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}
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bool UnwReadH(const uint32_t a, uint16_t *v) {
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if (!validate_addr(a))
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return false;
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*v = *(uint16_t *)a;
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return true;
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}
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bool UnwReadB(const uint32_t a, uint8_t *v) {
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if (!validate_addr(a))
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return false;
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*v = *(uint8_t *)a;
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return true;
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}
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#endif // __arm__ || __thumb__
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