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250 lines
7.6 KiB
250 lines
7.6 KiB
/**
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* Marlin 3D Printer Firmware
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* Copyright (c) 2020 MarlinFirmware [https://github.com/MarlinFirmware/Marlin]
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*
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* Based on Sprinter and grbl.
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* Copyright (c) 2011 Camiel Gubbels / Erik van der Zalm
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <https://www.gnu.org/licenses/>.
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*
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*/
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#include "../../../inc/MarlinConfig.h"
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#if HAS_FSMC_TFT
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#include "tft_fsmc.h"
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#include <libmaple/fsmc.h>
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#include <libmaple/gpio.h>
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#include <libmaple/dma.h>
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LCD_CONTROLLER_TypeDef *TFT_FSMC::LCD;
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/**
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* FSMC LCD IO
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*/
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#define __ASM __asm
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#define __STATIC_INLINE static inline
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__attribute__((always_inline)) __STATIC_INLINE void __DSB() {
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__ASM volatile ("dsb 0xF":::"memory");
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}
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#define FSMC_CS_NE1 PD7
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#if ENABLED(STM32_XL_DENSITY)
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#define FSMC_CS_NE2 PG9
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#define FSMC_CS_NE3 PG10
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#define FSMC_CS_NE4 PG12
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#define FSMC_RS_A0 PF0
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#define FSMC_RS_A1 PF1
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#define FSMC_RS_A2 PF2
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#define FSMC_RS_A3 PF3
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#define FSMC_RS_A4 PF4
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#define FSMC_RS_A5 PF5
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#define FSMC_RS_A6 PF12
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#define FSMC_RS_A7 PF13
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#define FSMC_RS_A8 PF14
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#define FSMC_RS_A9 PF15
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#define FSMC_RS_A10 PG0
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#define FSMC_RS_A11 PG1
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#define FSMC_RS_A12 PG2
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#define FSMC_RS_A13 PG3
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#define FSMC_RS_A14 PG4
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#define FSMC_RS_A15 PG5
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#endif
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#define FSMC_RS_A16 PD11
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#define FSMC_RS_A17 PD12
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#define FSMC_RS_A18 PD13
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#define FSMC_RS_A19 PE3
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#define FSMC_RS_A20 PE4
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#define FSMC_RS_A21 PE5
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#define FSMC_RS_A22 PE6
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#define FSMC_RS_A23 PE2
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#if ENABLED(STM32_XL_DENSITY)
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#define FSMC_RS_A24 PG13
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#define FSMC_RS_A25 PG14
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#endif
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/* Timing configuration */
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#define FSMC_ADDRESS_SETUP_TIME 15 // AddressSetupTime
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#define FSMC_DATA_SETUP_TIME 15 // DataSetupTime
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static uint8_t fsmcInit = 0;
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void TFT_FSMC::Init() {
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uint8_t cs = FSMC_CS_PIN, rs = FSMC_RS_PIN;
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uint32_t controllerAddress;
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#if PIN_EXISTS(TFT_BACKLIGHT)
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OUT_WRITE(TFT_BACKLIGHT_PIN, DISABLED(DELAYED_BACKLIGHT_INIT));
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#endif
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#if ENABLED(LCD_USE_DMA_FSMC)
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dma_init(FSMC_DMA_DEV);
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dma_disable(FSMC_DMA_DEV, FSMC_DMA_CHANNEL);
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dma_set_priority(FSMC_DMA_DEV, FSMC_DMA_CHANNEL, DMA_PRIORITY_MEDIUM);
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#endif
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#if PIN_EXISTS(TFT_RESET)
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OUT_WRITE(TFT_RESET_PIN, HIGH);
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delay(100);
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#endif
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#if PIN_EXISTS(TFT_BACKLIGHT)
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OUT_WRITE(TFT_BACKLIGHT_PIN, HIGH);
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#endif
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struct fsmc_nor_psram_reg_map* fsmcPsramRegion;
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if (fsmcInit) return;
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fsmcInit = 1;
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switch (cs) {
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case FSMC_CS_NE1: controllerAddress = (uint32_t)FSMC_NOR_PSRAM_REGION1; fsmcPsramRegion = FSMC_NOR_PSRAM1_BASE; break;
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#if ENABLED(STM32_XL_DENSITY)
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case FSMC_CS_NE2: controllerAddress = (uint32_t)FSMC_NOR_PSRAM_REGION2; fsmcPsramRegion = FSMC_NOR_PSRAM2_BASE; break;
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case FSMC_CS_NE3: controllerAddress = (uint32_t)FSMC_NOR_PSRAM_REGION3; fsmcPsramRegion = FSMC_NOR_PSRAM3_BASE; break;
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case FSMC_CS_NE4: controllerAddress = (uint32_t)FSMC_NOR_PSRAM_REGION4; fsmcPsramRegion = FSMC_NOR_PSRAM4_BASE; break;
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#endif
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default: return;
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}
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#define _ORADDR(N) controllerAddress |= (_BV32(N) - 2)
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switch (rs) {
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#if ENABLED(STM32_XL_DENSITY)
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case FSMC_RS_A0: _ORADDR( 1); break;
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case FSMC_RS_A1: _ORADDR( 2); break;
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case FSMC_RS_A2: _ORADDR( 3); break;
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case FSMC_RS_A3: _ORADDR( 4); break;
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case FSMC_RS_A4: _ORADDR( 5); break;
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case FSMC_RS_A5: _ORADDR( 6); break;
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case FSMC_RS_A6: _ORADDR( 7); break;
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case FSMC_RS_A7: _ORADDR( 8); break;
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case FSMC_RS_A8: _ORADDR( 9); break;
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case FSMC_RS_A9: _ORADDR(10); break;
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case FSMC_RS_A10: _ORADDR(11); break;
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case FSMC_RS_A11: _ORADDR(12); break;
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case FSMC_RS_A12: _ORADDR(13); break;
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case FSMC_RS_A13: _ORADDR(14); break;
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case FSMC_RS_A14: _ORADDR(15); break;
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case FSMC_RS_A15: _ORADDR(16); break;
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#endif
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case FSMC_RS_A16: _ORADDR(17); break;
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case FSMC_RS_A17: _ORADDR(18); break;
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case FSMC_RS_A18: _ORADDR(19); break;
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case FSMC_RS_A19: _ORADDR(20); break;
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case FSMC_RS_A20: _ORADDR(21); break;
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case FSMC_RS_A21: _ORADDR(22); break;
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case FSMC_RS_A22: _ORADDR(23); break;
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case FSMC_RS_A23: _ORADDR(24); break;
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#if ENABLED(STM32_XL_DENSITY)
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case FSMC_RS_A24: _ORADDR(25); break;
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case FSMC_RS_A25: _ORADDR(26); break;
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#endif
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default: return;
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}
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rcc_clk_enable(RCC_FSMC);
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gpio_set_mode(GPIOD, 14, GPIO_AF_OUTPUT_PP); // FSMC_D00
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gpio_set_mode(GPIOD, 15, GPIO_AF_OUTPUT_PP); // FSMC_D01
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gpio_set_mode(GPIOD, 0, GPIO_AF_OUTPUT_PP); // FSMC_D02
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gpio_set_mode(GPIOD, 1, GPIO_AF_OUTPUT_PP); // FSMC_D03
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gpio_set_mode(GPIOE, 7, GPIO_AF_OUTPUT_PP); // FSMC_D04
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gpio_set_mode(GPIOE, 8, GPIO_AF_OUTPUT_PP); // FSMC_D05
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gpio_set_mode(GPIOE, 9, GPIO_AF_OUTPUT_PP); // FSMC_D06
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gpio_set_mode(GPIOE, 10, GPIO_AF_OUTPUT_PP); // FSMC_D07
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gpio_set_mode(GPIOE, 11, GPIO_AF_OUTPUT_PP); // FSMC_D08
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gpio_set_mode(GPIOE, 12, GPIO_AF_OUTPUT_PP); // FSMC_D09
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gpio_set_mode(GPIOE, 13, GPIO_AF_OUTPUT_PP); // FSMC_D10
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gpio_set_mode(GPIOE, 14, GPIO_AF_OUTPUT_PP); // FSMC_D11
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gpio_set_mode(GPIOE, 15, GPIO_AF_OUTPUT_PP); // FSMC_D12
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gpio_set_mode(GPIOD, 8, GPIO_AF_OUTPUT_PP); // FSMC_D13
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gpio_set_mode(GPIOD, 9, GPIO_AF_OUTPUT_PP); // FSMC_D14
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gpio_set_mode(GPIOD, 10, GPIO_AF_OUTPUT_PP); // FSMC_D15
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gpio_set_mode(GPIOD, 4, GPIO_AF_OUTPUT_PP); // FSMC_NOE
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gpio_set_mode(GPIOD, 5, GPIO_AF_OUTPUT_PP); // FSMC_NWE
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gpio_set_mode(PIN_MAP[cs].gpio_device, PIN_MAP[cs].gpio_bit, GPIO_AF_OUTPUT_PP); //FSMC_CS_NEx
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gpio_set_mode(PIN_MAP[rs].gpio_device, PIN_MAP[rs].gpio_bit, GPIO_AF_OUTPUT_PP); //FSMC_RS_Ax
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fsmcPsramRegion->BCR = FSMC_BCR_WREN | FSMC_BCR_MTYP_SRAM | FSMC_BCR_MWID_16BITS | FSMC_BCR_MBKEN;
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fsmcPsramRegion->BTR = (FSMC_DATA_SETUP_TIME << 8) | FSMC_ADDRESS_SETUP_TIME;
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afio_remap(AFIO_REMAP_FSMC_NADV);
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LCD = (LCD_CONTROLLER_TypeDef*)controllerAddress;
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}
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void TFT_FSMC::Transmit(uint16_t Data) {
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LCD->RAM = Data;
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__DSB();
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}
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void TFT_FSMC::WriteReg(uint16_t Reg) {
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LCD->REG = Reg;
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__DSB();
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}
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uint32_t TFT_FSMC::GetID() {
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uint32_t id;
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WriteReg(0x0000);
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id = LCD->RAM;
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if (id == 0)
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id = ReadID(LCD_READ_ID);
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if ((id & 0xFFFF) == 0 || (id & 0xFFFF) == 0xFFFF)
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id = ReadID(LCD_READ_ID4);
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if ((id & 0xFF00) == 0 && (id & 0xFF) != 0)
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id = ReadID(LCD_READ_ID4);
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return id;
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}
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uint32_t TFT_FSMC::ReadID(uint16_t Reg) {
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uint32_t id;
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WriteReg(Reg);
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id = LCD->RAM; // dummy read
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id = Reg << 24;
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id |= (LCD->RAM & 0x00FF) << 16;
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id |= (LCD->RAM & 0x00FF) << 8;
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id |= LCD->RAM & 0x00FF;
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return id;
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}
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bool TFT_FSMC::isBusy() {
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return false;
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}
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void TFT_FSMC::Abort() {
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}
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void TFT_FSMC::TransmitDMA(uint32_t MemoryIncrease, uint16_t *Data, uint16_t Count) {
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#if defined(FSMC_DMA_DEV) && defined(FSMC_DMA_CHANNEL)
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dma_setup_transfer(FSMC_DMA_DEV, FSMC_DMA_CHANNEL, Data, DMA_SIZE_16BITS, &LCD->RAM, DMA_SIZE_16BITS, DMA_MEM_2_MEM | MemoryIncrease);
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dma_set_num_transfers(FSMC_DMA_DEV, FSMC_DMA_CHANNEL, Count);
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dma_clear_isr_bits(FSMC_DMA_DEV, FSMC_DMA_CHANNEL);
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dma_enable(FSMC_DMA_DEV, FSMC_DMA_CHANNEL);
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while ((dma_get_isr_bits(FSMC_DMA_DEV, FSMC_DMA_CHANNEL) & 0x0A) == 0) {};
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dma_disable(FSMC_DMA_DEV, FSMC_DMA_CHANNEL);
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#endif
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}
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#endif // HAS_FSMC_TFT
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