Scott Lahteine
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9b1c0a75e1
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🎨 Rename HAL timer elements
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3 years ago |
Scott Lahteine
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69917690f3
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Adjust HAL platform defines, comments
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4 years ago |
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Scott Lahteine
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4d1357e318
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Adjust HAL platform defines, comments
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4 years ago |
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Scott Lahteine
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4e8eea8e78
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Adjust HAL platform defines, comments
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4 years ago |
Diego von Deschwanden
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42fbd527f3
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Fix links to secure sites (#18745)
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4 years ago |
ellensp
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33d1e77e2e
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Allow pins override of *_TIMER_NUM and HAL_*_TIMER_ISR (#18128)
Co-authored-by: Scott Lahteine <github@thinkyhead.com>
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4 years ago |
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Scott Lahteine
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6bead0c1b0
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Shorter paths to HAL, ExtUI (#17156)
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4 years ago |
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Scott Lahteine
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bfad23d3e2
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(c) 2020
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4 years ago |
Lino Barreca
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ac71cdc265
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New HardwareTimer for STM32 5.7.0 (#15655)
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5 years ago |
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Scott Lahteine
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f01f0d1956
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Drop C-style 'void' argument
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5 years ago |
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Scott Lahteine
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75efa3cdac
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Reorganize HAL (#14832)
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5 years ago |
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Scott Lahteine
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93cd66ac11
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Tweaky change from (C) to (c)
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5 years ago |
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Scott Lahteine
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26de051e92
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HAL SPI pin init cleanup
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5 years ago |
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Scott Lahteine
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3a1b6fe8c1
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Coding standards
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5 years ago |
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Scott Lahteine
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0feeef2604
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Update copyright in headers
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5 years ago |
etagle
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0566badcef
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Add memory barrier, optimal interrupt on-off
Disabling an ISR on ARM has 3 instructions of latency. A Memory barrier is REQUIRED to ensure proper and predictable disabling. Memory barriers are expensive, so avoid disabling if already disabled (See https://mcuoneclipse.com/2015/10/16/nvic-disabling-interrupts-on-arm-cortex-m-and-the-need-for-a-memory-barrier-instruction/)
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6 years ago |
Chris Pepper
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cc6d41e1d3
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Use a macro for HAL header redirection (#10380)
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6 years ago |
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Scott Lahteine
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ac368f2788
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Add STEPPER_ISR_ENABLED() to HALs
Some also get a `HAL_timer_interrupt_enabled` function.
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6 years ago |
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Scott Lahteine
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c2b1d51f16
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HAL whitespace and style cleanup
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7 years ago |
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Scott Lahteine
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2af62a5d8d
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Apply spacing, const to some HAL code
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7 years ago |
teemuatlut
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f3e562e46e
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HAL for 32-bit Teensy (3.5, 3.6) architecture
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7 years ago |
