Tree: 22771dd2dd

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2.0.8.1

2.0.9.1

2.0.9.2

2.0.9.3

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Commit Graph

9 Commits (22771dd2dd804b08ccd37d8d6f85888dfbbba111)

Author	SHA1	Message	Date
etagle	569df3fc0c	Fix interrupt-based endstop detection - Also implemented real endstop reading on interrupt.	6 years ago
etagle	0566badcef	Add memory barrier, optimal interrupt on-off Disabling an ISR on ARM has 3 instructions of latency. A Memory barrier is REQUIRED to ensure proper and predictable disabling. Memory barriers are expensive, so avoid disabling if already disabled (See https://mcuoneclipse.com/2015/10/16/nvic-disabling-interrupts-on-arm-cortex-m-and-the-need-for-a-memory-barrier-instruction/)	6 years ago
Scott Lahteine	37b15fe4cf	Reorder HAL timer header items	6 years ago
Scott Lahteine	456cf971af	HAL FastIO cleanup and fixes	6 years ago
Scott Lahteine	a3ce8a3fcd	Add sanity checks for EMERGENCY_PARSER	6 years ago
Eduardo José Tagle	0c428a66d9	Proper AVR preemptive interrupt handling (#10496) Also simplify logic on all ARM-based interrupts. Now, it is REQUIRED to properly configure interrupt priority. USART should have highest priority, followed by Stepper, and then all others.	6 years ago
Scott Lahteine	f423e54f77	Strip trailing spaces	6 years ago
Scott Lahteine	dea686cf55	Define short pin names in fastio for STM32 (#10461)	6 years ago
Karl Andersson	428c54f2ad	[2.0.x] HAL for STM32F4 (#10434)	6 years ago