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@ -77,113 +77,119 @@ |
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#ifdef TARGET_LPC1768 |
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#ifdef TARGET_LPC1768 |
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#include <U8glib.h> |
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#include "../../inc/MarlinConfigPre.h" |
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#define I2C_SLA (0x3C*2) |
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//#define I2C_CMD_MODE 0x080
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#define I2C_CMD_MODE 0x000 |
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#define I2C_DATA_MODE 0x040 |
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//#define U8G_I2C_OPT_FAST 16
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uint8_t u8g_com_ssd_I2C_start_sequence(u8g_t *u8g) { |
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/* are we requested to set the a0 state? */ |
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if (u8g->pin_list[U8G_PI_SET_A0] == 0) return 1; |
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/* setup bus, might be a repeated start */ |
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if (u8g_i2c_start(I2C_SLA) == 0) |
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return 0; |
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if (u8g->pin_list[U8G_PI_A0_STATE] == 0 ) { |
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if (u8g_i2c_send_byte(I2C_CMD_MODE) == 0) return 0; |
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} |
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else if (u8g_i2c_send_byte(I2C_DATA_MODE) == 0) |
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return 0; |
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u8g->pin_list[U8G_PI_SET_A0] = 0; |
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return 1; |
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} |
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uint8_t u8g_com_HAL_LPC1768_ssd_hw_i2c_fn(u8g_t *u8g, uint8_t msg, uint8_t arg_val, void *arg_ptr) { |
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#if ENABLED(DOGLCD) |
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switch(msg) { |
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case U8G_COM_MSG_INIT: |
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//u8g_com_arduino_digital_write(u8g, U8G_PI_SCL, HIGH);
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//u8g_com_arduino_digital_write(u8g, U8G_PI_SDA, HIGH);
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//u8g->pin_list[U8G_PI_A0_STATE] = 0; /* inital RS state: unknown mode */
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u8g_i2c_init(u8g->pin_list[U8G_PI_I2C_OPTION]); |
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u8g_com_ssd_I2C_start_sequence(u8g); |
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break; |
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case U8G_COM_MSG_STOP: |
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break; |
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case U8G_COM_MSG_RESET: |
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/* Currently disabled, but it could be enable. Previous restrictions have been removed */ |
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/* u8g_com_arduino_digital_write(u8g, U8G_PI_RESET, arg_val); */ |
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break; |
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case U8G_COM_MSG_CHIP_SELECT: |
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u8g->pin_list[U8G_PI_A0_STATE] = 0; |
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u8g->pin_list[U8G_PI_SET_A0] = 1; /* force a0 to set again, also forces start condition */ |
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if (arg_val == 0 ) { |
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/* disable chip, send stop condition */ |
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u8g_i2c_stop(); |
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} |
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else { |
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/* enable, do nothing: any byte writing will trigger the i2c start */ |
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} |
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break; |
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case U8G_COM_MSG_WRITE_BYTE: |
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#include <U8glib.h> |
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//u8g->pin_list[U8G_PI_SET_A0] = 1;
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//if (u8g_com_arduino_ssd_start_sequence(u8g) == 0)
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#define I2C_SLA (0x3C*2) |
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// return u8g_i2c_stop(), 0;
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//#define I2C_CMD_MODE 0x080
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if (u8g_i2c_send_byte(arg_val) == 0) |
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#define I2C_CMD_MODE 0x000 |
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return u8g_i2c_stop(), 0; |
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#define I2C_DATA_MODE 0x040 |
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// u8g_i2c_stop();
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break; |
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//#define U8G_I2C_OPT_FAST 16
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uint8_t u8g_com_ssd_I2C_start_sequence(u8g_t *u8g) { |
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/* are we requested to set the a0 state? */ |
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if (u8g->pin_list[U8G_PI_SET_A0] == 0) return 1; |
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case U8G_COM_MSG_WRITE_SEQ: { |
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/* setup bus, might be a repeated start */ |
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if (u8g_i2c_start(I2C_SLA) == 0) |
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return 0; |
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if (u8g->pin_list[U8G_PI_A0_STATE] == 0 ) { |
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if (u8g_i2c_send_byte(I2C_CMD_MODE) == 0) return 0; |
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} |
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else if (u8g_i2c_send_byte(I2C_DATA_MODE) == 0) |
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return 0; |
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u8g->pin_list[U8G_PI_SET_A0] = 0; |
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return 1; |
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} |
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uint8_t u8g_com_HAL_LPC1768_ssd_hw_i2c_fn(u8g_t *u8g, uint8_t msg, uint8_t arg_val, void *arg_ptr) { |
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switch(msg) { |
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case U8G_COM_MSG_INIT: |
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//u8g_com_arduino_digital_write(u8g, U8G_PI_SCL, HIGH);
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//u8g_com_arduino_digital_write(u8g, U8G_PI_SDA, HIGH);
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//u8g->pin_list[U8G_PI_A0_STATE] = 0; /* inital RS state: unknown mode */
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u8g_i2c_init(u8g->pin_list[U8G_PI_I2C_OPTION]); |
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u8g_com_ssd_I2C_start_sequence(u8g); |
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break; |
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case U8G_COM_MSG_STOP: |
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break; |
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case U8G_COM_MSG_RESET: |
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/* Currently disabled, but it could be enable. Previous restrictions have been removed */ |
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/* u8g_com_arduino_digital_write(u8g, U8G_PI_RESET, arg_val); */ |
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break; |
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case U8G_COM_MSG_CHIP_SELECT: |
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u8g->pin_list[U8G_PI_A0_STATE] = 0; |
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u8g->pin_list[U8G_PI_SET_A0] = 1; /* force a0 to set again, also forces start condition */ |
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if (arg_val == 0 ) { |
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/* disable chip, send stop condition */ |
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u8g_i2c_stop(); |
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} |
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else { |
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/* enable, do nothing: any byte writing will trigger the i2c start */ |
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} |
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break; |
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case U8G_COM_MSG_WRITE_BYTE: |
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//u8g->pin_list[U8G_PI_SET_A0] = 1;
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//if (u8g_com_arduino_ssd_start_sequence(u8g) == 0)
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// return u8g_i2c_stop(), 0;
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if (u8g_i2c_send_byte(arg_val) == 0) |
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return u8g_i2c_stop(), 0; |
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// u8g_i2c_stop();
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break; |
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case U8G_COM_MSG_WRITE_SEQ: { |
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//u8g->pin_list[U8G_PI_SET_A0] = 1;
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if (u8g_com_ssd_I2C_start_sequence(u8g) == 0) |
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return u8g_i2c_stop(), 0; |
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register uint8_t *ptr = (uint8_t *)arg_ptr; |
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while (arg_val > 0) { |
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if (u8g_i2c_send_byte(*ptr++) == 0) |
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return u8g_i2c_stop(), 0; |
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arg_val--; |
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} |
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} |
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// u8g_i2c_stop();
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break; |
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case U8G_COM_MSG_WRITE_SEQ_P: { |
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//u8g->pin_list[U8G_PI_SET_A0] = 1;
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//u8g->pin_list[U8G_PI_SET_A0] = 1;
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if (u8g_com_ssd_I2C_start_sequence(u8g) == 0) |
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if (u8g_com_ssd_I2C_start_sequence(u8g) == 0) |
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return u8g_i2c_stop(), 0; |
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return u8g_i2c_stop(), 0; |
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register uint8_t *ptr = (uint8_t *)arg_ptr; |
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register uint8_t *ptr = (uint8_t *)arg_ptr; |
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while (arg_val > 0) { |
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while (arg_val > 0) { |
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if (u8g_i2c_send_byte(*ptr++) == 0) |
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if (u8g_i2c_send_byte(u8g_pgm_read(ptr)) == 0) |
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return u8g_i2c_stop(), 0; |
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return 0; |
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arg_val--; |
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ptr++; |
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} |
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arg_val--; |
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} |
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} |
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// u8g_i2c_stop();
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} |
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break; |
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// u8g_i2c_stop();
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break; |
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case U8G_COM_MSG_WRITE_SEQ_P: { |
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case U8G_COM_MSG_ADDRESS: /* define cmd (arg_val = 0) or data mode (arg_val = 1) */ |
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//u8g->pin_list[U8G_PI_SET_A0] = 1;
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u8g->pin_list[U8G_PI_A0_STATE] = arg_val; |
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if (u8g_com_ssd_I2C_start_sequence(u8g) == 0) |
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u8g->pin_list[U8G_PI_SET_A0] = 1; /* force a0 to set again */ |
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return u8g_i2c_stop(), 0; |
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register uint8_t *ptr = (uint8_t *)arg_ptr; |
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while (arg_val > 0) { |
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if (u8g_i2c_send_byte(u8g_pgm_read(ptr)) == 0) |
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return 0; |
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ptr++; |
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arg_val--; |
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} |
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} |
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// u8g_i2c_stop();
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break; |
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case U8G_COM_MSG_ADDRESS: /* define cmd (arg_val = 0) or data mode (arg_val = 1) */ |
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u8g_i2c_start(0); // send slave address and write bit
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u8g->pin_list[U8G_PI_A0_STATE] = arg_val; |
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u8g_i2c_send_byte(arg_val ? 0x40 : 0x80); // Write to ? Graphics DRAM mode : Command mode
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u8g->pin_list[U8G_PI_SET_A0] = 1; /* force a0 to set again */ |
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break; |
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u8g_i2c_start(0); // send slave address and write bit
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} // switch
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u8g_i2c_send_byte(arg_val ? 0x40 : 0x80); // Write to ? Graphics DRAM mode : Command mode
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return 1; |
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break; |
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} |
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} // switch
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#endif // DOGLCD
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return 1; |
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} |
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#endif // TARGET_LPC1768
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#endif // TARGET_LPC1768
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