From d76c608f29ca6dd7d9f9667d7219d07a08a5591b Mon Sep 17 00:00:00 2001 From: Sergey Date: Wed, 8 Apr 2020 11:38:40 +0300 Subject: [PATCH] =?UTF-8?q?=D0=94=D1=80=D0=B0=D0=B9=D0=B2=D0=B5=D1=80=20SD?= =?UTF-8?q?IO?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- Marlin/src/libs/fatfs/diskio.cpp | 31 +- Marlin/src/libs/fatfs/diskio.h | 1 + Marlin/src/libs/fatfs/sdio_driver.cpp | 291 ++++++++++++ Marlin/src/libs/fatfs/sdio_driver.h | 144 ++++++ Marlin/src/module/mks_wifi/mks_wifi.cpp | 5 +- Marlin/src/module/mks_wifi/mks_wifi_sd.cpp | 108 ++--- Marlin/src/module/mks_wifi/mks_wifi_sd.h | 12 +- .../module/mks_wifi/mks_wifi_sd_low_lev.cpp | 12 +- .../src/module/mks_wifi/mks_wifi_sd_low_lev.h | 4 + .../src/module/mks_wifi/mks_wifi_settings.h | 4 + Marlin/src/module/mks_wifi/small_cmsis.h | 417 +++++++++++++++++- 11 files changed, 917 insertions(+), 112 deletions(-) create mode 100644 Marlin/src/libs/fatfs/sdio_driver.cpp create mode 100644 Marlin/src/libs/fatfs/sdio_driver.h diff --git a/Marlin/src/libs/fatfs/diskio.cpp b/Marlin/src/libs/fatfs/diskio.cpp index a2a8fe22d1..d15ff9204b 100755 --- a/Marlin/src/libs/fatfs/diskio.cpp +++ b/Marlin/src/libs/fatfs/diskio.cpp @@ -42,7 +42,7 @@ DSTATUS disk_initialize ( int result; if(pdrv == DEV_SD){ - result=sd_init(); + result=SD_Init(); if(result != 0) { return STA_NOINIT; }; @@ -67,12 +67,15 @@ DRESULT disk_read ( uint8_t res=0; if(pdrv == DEV_SD){ - res=sd_read((uint8_t*)buff,sector,count); - if(res){ - return RES_ERROR; - }else{ - return RES_OK; - } + //1st read + res=SD_transfer((uint8_t *)buff, (uint32_t) sector, count, SD2UM); + if(res != 0){ + res=SD_transfer((uint8_t *)buff, (uint32_t) sector, count, SD2UM); + if(res != 0){ + return RES_ERROR; + }; + }; + return RES_OK; }; return RES_PARERR; } @@ -93,12 +96,14 @@ DRESULT disk_write ( uint8_t res; if(pdrv == DEV_SD){ - res=sd_write((uint8_t*)buff,sector,count); - if(res){ - return RES_ERROR; - }else{ - return RES_OK; - } + res=SD_transfer((uint8_t *)buff, (uint32_t) sector, count, UM2SD); + if(res != 0){ + res=SD_transfer((uint8_t *)buff, (uint32_t) sector, count, UM2SD); + if(res != 0){ + return RES_ERROR; + }; + }; + return RES_OK; }; return RES_PARERR; } diff --git a/Marlin/src/libs/fatfs/diskio.h b/Marlin/src/libs/fatfs/diskio.h index bdb91a83e1..3d8c459e2f 100755 --- a/Marlin/src/libs/fatfs/diskio.h +++ b/Marlin/src/libs/fatfs/diskio.h @@ -11,6 +11,7 @@ #include "integer.h" #include "../../module/mks_wifi/mks_wifi_sd_low_lev.h" +#include "sdio_driver.h" #include "../../MarlinCore.h" /* Status of Disk Functions */ diff --git a/Marlin/src/libs/fatfs/sdio_driver.cpp b/Marlin/src/libs/fatfs/sdio_driver.cpp new file mode 100644 index 0000000000..09ab05475d --- /dev/null +++ b/Marlin/src/libs/fatfs/sdio_driver.cpp @@ -0,0 +1,291 @@ +#include "sdio_driver.h" + +volatile SDCard_TypeDef SDCard; +volatile SD_Status_TypeDef SDStatus; +volatile uint32_t response[4]; //Для хранения ответа от карты +volatile uint8_t transmit; //Флаг запущенной передачи данных в SDIO +volatile uint8_t state=0; //Для хранения состояния карты +volatile uint8_t multiblock=0; //Используется в прерывании SDIO, чтоб слать команду STOP +volatile uint32_t error_flag=0; + +volatile uint8_t __attribute__ ((aligned (4))) buf_copy[8*1024]; + + +void SD_check_status(SD_Status_TypeDef* SDStatus,uint32_t* reg){ + SDStatus->ake_seq_error = (*reg & (1 << 3)) ? 1 : 0; + SDStatus->app_cmd = (*reg & (1 << 5)) ? 1 : 0; + SDStatus->ready_for_data = (*reg & (1 << 8)) ? 1 : 0; + SDStatus->current_state = (uint8_t)((*reg & (0x0F << 9)) >> 9); + SDStatus->erase_reset = (*reg & (1 << 13)) ? 1 : 0; + SDStatus->card_ecc_disabled = (*reg & (1 << 14)) ? 1 : 0; + SDStatus->wp_erase_skip = (*reg & (1 << 15)) ? 1 : 0; + SDStatus->csd_overwrite = (*reg & (1 << 16)) ? 1 : 0; + SDStatus->error = (*reg & (1 << 19)) ? 1 : 0; + SDStatus->cc_error = (*reg & (1 << 20)) ? 1 : 0; + SDStatus->card_ecc_failed = (*reg & (1 << 21)) ? 1 : 0; + SDStatus->illegal_command = (*reg & (1 << 22)) ? 1 : 0; + SDStatus->com_crc_error = (*reg & (1 << 23)) ? 1 : 0; + SDStatus->lock_unlock_failed= (*reg & (1 << 24)) ? 1 : 0; + SDStatus->card_is_locked = (*reg & (1 << 25)) ? 1 : 0; + SDStatus->wp_violation = (*reg & (1 << 26)) ? 1 : 0; + SDStatus->erase_param = (*reg & (1 << 27)) ? 1 : 0; + SDStatus->erase_seq_error = (*reg & (1 << 28)) ? 1 : 0; + SDStatus->block_len_error = (*reg & (1 << 29)) ? 1 : 0; + SDStatus->address_error = (*reg & (1 << 30)) ? 1 : 0; + SDStatus->out_of_range = (*reg & (1U << 31)) ? 1 : 0; +}; + +uint8_t SD_Cmd(uint8_t cmd, uint32_t arg, uint16_t response_type, uint32_t *response){ + SDIO->ICR = SDIO_ICR_CMD_FLAGS; + SDIO->ARG = arg; + SDIO->CMD = (uint32_t)(response_type | cmd); + SDIO->CMD |= SDIO_CMD_CPSMEN; + + while( (SDIO->STA & SDIO_STA_CMD_FLAGS) == 0){asm("nop");}; + + if (response_type != SDIO_RESP_NONE) { + response[0] = SDIO->RESP1; + response[1] = SDIO->RESP2; + response[2] = SDIO->RESP3; + response[3] = SDIO->RESP4; + } + + if (SDIO->STA & SDIO_STA_CTIMEOUT) { + return 2; + } + if (SDIO->STA & SDIO_STA_CCRCFAIL) { + return 3; + } + return 0; +} + +//#pragma GCC push_options +//#pragma GCC optimize ("O0") +uint32_t SD_transfer(uint8_t *buf, uint32_t blk, uint32_t cnt, uint32_t dir){ + uint32_t trials; + uint8_t cmd=0; + uint8_t *ptr = buf; + + trials=SDIO_DATA_TIMEOUT; + while (transmit && trials--) {}; + if(!trials) { + return 1; + } + + state=0; + while(state != 4){ //Дождаться когда карта будет в режиме tran (4) + SD_Cmd(SD_CMD13, SDCard.RCA ,SDIO_RESP_SHORT,(uint32_t*)response); + SD_check_status((SD_Status_TypeDef*)&SDStatus,(uint32_t*)&response[0]); + state=SDStatus.current_state; + + if((state == 5) || (state == 6)) SD_Cmd(SD_CMD12, 0, SDIO_RESP_SHORT,(uint32_t*)response); + }; + + + //Выключить DMA + DMA2->IFCR=DMA_S4_CLEAR; + DMA2_Channel4->CCR=0; + DMA2->IFCR=DMA_S4_CLEAR; + DMA2_Channel4->CCR=DMA_SDIO_CR; + + multiblock = (cnt == 1) ? 0 : 1; + if (dir==UM2SD){ //Запись + if(((uint32_t)buf % 4) != 0){ + DEBUG("Buffer not aligned"); + memcpy((uint8_t*)buf_copy,buf,cnt*512); + ptr=(uint8_t*)buf_copy; + }; + DMA2_Channel4->CCR|=(0x01 << DMA_CCR_DIR_Pos); + cmd=(cnt == 1)? SD_CMD24 : SD_CMD25; + } + else if (dir==SD2UM){ //Чтение + cmd=(cnt == 1)? SD_CMD17 : SD_CMD18; + if(((uint32_t)buf % 4) != 0){ + ptr=(uint8_t*)buf_copy; + }; + }; + + DMA2_Channel4->CMAR=(uint32_t)ptr; //Memory address + DMA2_Channel4->CPAR=(uint32_t)&(SDIO->FIFO); //SDIO FIFO Address + DMA2_Channel4->CNDTR=cnt*512/4; + + transmit=1; + error_flag=0; + + DISABLE_IRQ; + SD_Cmd(cmd, blk, SDIO_RESP_SHORT, (uint32_t*)response); + + SDIO->ICR=SDIO_ICR_DATA_FLAGS; + SDIO->DTIMER=(uint32_t)0x6BDD00; + SDIO->DLEN=cnt*512; //Количество байт (блок 512 байт) + SDIO->DCTRL= SDIO_DCTRL | (dir & SDIO_DCTRL_DTDIR); //Direction. 0=Controller to card, 1=Card to Controller + + DMA2_Channel4->CCR |= DMA_CCR_EN; + SDIO->DCTRL|=1; //DPSM is enabled + ENABLE_IRQ; + + while((SDIO->STA & (SDIO_STA_DATAEND|SDIO_STA_ERRORS)) == 0){__asm volatile ("nop");}; + + if(SDIO->STA & SDIO_STA_ERRORS){ + error_flag=SDIO->STA; + transmit=0; + SDIO->ICR = SDIO_ICR_STATIC; + DMA2_Channel4->CCR = 0; + DMA2->IFCR = DMA_S4_CLEAR; + return error_flag; + } + + if(dir==SD2UM) { //Read + while (DMA2_Channel4->CCR & DMA_CCR_EN) { + if(SDIO->STA & SDIO_STA_ERRORS) { + transmit=0; + return 99; + } + DMA2_Channel4->CCR = 0; + DMA2->IFCR = DMA_S4_CLEAR; + }; + + if(((uint32_t)buf % 4) != 0){ + memcpy(buf,(uint8_t*)buf_copy,cnt*512); + } + }; + + + + if(multiblock > 0) SD_Cmd(SD_CMD12, 0, SDIO_RESP_SHORT, (uint32_t*)response); + transmit=0; + DMA2->IFCR = DMA_S4_CLEAR; + SDIO->ICR=SDIO_ICR_STATIC; + return 0; +}; +//#pragma GCC pop_options + +uint8_t SD_Init(void) { + volatile uint32_t trials = 0x0000FFFF; + uint32_t tempreg; //Для временного хранения регистров + uint8_t result = 0; + + RCC->AHBENR |= RCC_AHBENR_SDIOEN | RCC_AHBENR_DMA2EN; + + SDIO->CLKCR = SDIO_CLKCR_CLKEN | (58 << SDIO_CLKCR_CLKDIV_Pos); + SDIO->POWER |= SDIO_POWER_PWRCTRL; + + + result = SD_Cmd(SD_CMD0,0x00,SDIO_RESP_NONE,(uint32_t*)response); //NORESP + if (result != 0){ + ERROR("CMD0: %d",result); + return 1; + }; + + result = SD_Cmd(SD_CMD8,SD_CHECK_PATTERN,SDIO_RESP_SHORT,(uint32_t*)response); //R7 + if (result != 0) { + ERROR("CMD8: %d",result); + return 8; + }; + if (response[0] != SD_CHECK_PATTERN) { + ERROR("CMD8 check"); + return 8; + }; + + trials = 0x0000FFFF; + while (--trials) { + SD_Cmd(SD_CMD55, 0 ,SDIO_RESP_SHORT,(uint32_t*)response); // CMD55 with RCA 0 R1 + SD_check_status((SD_Status_TypeDef*)&SDStatus,(uint32_t*)&response[0]); + SD_Cmd(SD_ACMD41,(1<<20|1<<30),SDIO_RESP_SHORT,(uint32_t*)response); + if (response[0] & SDIO_ACMD41_CHECK) break; + } + if (!trials) { + ERROR("CMD41 check"); + return 41; + }; + + result = SD_Cmd(SD_CMD2,0x00,SDIO_RESP_LONG,(uint32_t*)response); //CMD2 CID R2 + if (result != 0) { + ERROR("CMD2: %d",result); + return 2; + }; + + SDCard.CID[0]=response[0]; + SDCard.CID[1]=response[1]; + SDCard.CID[2]=response[2]; + SDCard.CID[3]=response[3]; + + result = SD_Cmd(SD_CMD3,0x00,SDIO_RESP_SHORT,(uint32_t*)response); //CMD3 RCA R6 + if (result != 0){ + ERROR("CMD3: %d",result); + return 3; + }; + + SDCard.RCA=( response[0] & (0xFFFF0000) ); + + result = SD_Cmd(SD_CMD9,SDCard.RCA,SDIO_RESP_LONG,(uint32_t*)response); //CMD9 СSD R2 + if (result != 0) { + ERROR("CMD9: %d",result); + return 9; + } + + SDCard.CSD[0]=response[0]; + SDCard.CSD[1]=response[1]; + SDCard.CSD[2]=response[2]; + SDCard.CSD[3]=response[3]; + + SD_parse_CSD((uint32_t*)SDCard.CSD); + + result = SD_Cmd(SD_CMD7,SDCard.RCA,SDIO_RESP_SHORT,(uint32_t*)response); //CMD7 tran R1b + SD_check_status((SD_Status_TypeDef*)&SDStatus,(uint32_t*)&response[0]); + if (result != 0) { + ERROR("CMD7: %d",result); + return 7; + } + + state=0; + //Дождаться когда карта будет в режиме tran (4) + while(state != 4){ + SD_Cmd(SD_CMD13, SDCard.RCA ,SDIO_RESP_SHORT,(uint32_t*)response); + SD_check_status((SD_Status_TypeDef*)&SDStatus,(uint32_t*)&response[0]); + state=SDStatus.current_state; + }; + + #if(SDIO_4BIT_Mode == 1) + result = SD_Cmd(SD_CMD55, SDCard.RCA ,SDIO_RESP_SHORT,(uint32_t*)response); //CMD55 with RCA + SD_check_status((SD_Status_TypeDef*)&SDStatus,(uint32_t*)&response[0]); + if (result != 0)return 55; + + result = SD_Cmd(6, 0x02, SDIO_RESP_SHORT,(uint32_t*)response); //Шлем ACMD6 c аргументом 0x02, установив 4-битный режим + if (result != 0) {return 6;}; + if (response[0] != 0x920) {return 5;}; //Убеждаемся, что карта находится в готовности работать с трансфером + + tempreg=((0x01)<CLKCR=tempreg; + + #if (SDIO_HIGH_SPEED != 0) + SD_HighSpeed(); + tempreg=((0x01)<CLKCR=tempreg; + #endif +#else + tempreg=0; + tempreg=SDIO_CLKCR_CLKEN; + SDIO->CLKCR=tempreg; +#endif + + DEBUG("SDINIT: ok"); + return 0; +}; + +void SD_parse_CSD(uint32_t* reg){ + uint32_t tmp; + //Версия CSD регистра + if(reg[0] & (11U << 30)){ + SDCard.CSDVer=2; + }else{ + SDCard.CSDVer=1; + }; + //Размер карты и количество блоков + tmp= (reg[2] >> 16) & 0xFFFF; + tmp |= (reg[1] & 0x3F) << 16; + SDCard.BlockCount=tmp*1000; + SDCard.Capacity=(tmp+1)*512; +}; + diff --git a/Marlin/src/libs/fatfs/sdio_driver.h b/Marlin/src/libs/fatfs/sdio_driver.h new file mode 100644 index 0000000000..475e3bb188 --- /dev/null +++ b/Marlin/src/libs/fatfs/sdio_driver.h @@ -0,0 +1,144 @@ +#ifndef SDIO_DRIVER_H +#define SDIO_DRIVER_H + +#include "../../module/mks_wifi/small_cmsis.h" +#include "../../module/mks_wifi/mks_wifi_sd_low_lev.h" + +// SD card description +typedef struct { + uint32_t Capacity; // Card capacity (MBytes for SDHC/SDXC, bytes otherwise) + uint32_t BlockCount; // SD card blocks count + uint32_t BlockSize; // SD card block size (bytes), determined in SD_ReadCSD() + uint32_t MaxBusClkFreq; // Maximum card bus frequency (MHz) + uint32_t RCA; // SD card RCA address (only for SDIO) + uint32_t PSN; // SD card serial number + uint32_t CSD[4]; // SD card CSD register (card structure data) + uint32_t CID[4]; // SD card CID register (card identification number) + uint16_t OID; // SD card OEM/Application ID + uint16_t MDT; // SD card manufacturing date + uint8_t Type; // Card type (detected by SD_Init()) + uint8_t CSDVer; // SD card CSD register version + uint8_t MID; // SD card manufacturer ID + uint8_t PNM[5]; // SD card product name (5-character ASCII string) + uint8_t PRV; // SD card product revision (two BCD digits: '6.2' will be 01100010b) + uint8_t SCR[8]; // SD card SCR register (SD card configuration) +} SDCard_TypeDef; + +typedef struct { + uint8_t out_of_range; //Аргумент команды вышел за пределы допустимого диапазона для этой карты. + uint8_t address_error; //Ошибочно выровненный адрес, который не соответствует длине блока, который использовался в команде. + uint8_t block_len_error; //Длина передаваемого блока не допустима для этой карты, или количество передаваемых байт не соответствует длине блока. + uint8_t erase_seq_error; //Произошла ошибка в последовательности команд стирания. + uint8_t erase_param; //Произошел недопустимый выбор записываемых блоков для стирания. + uint8_t wp_violation; //Устанавливается, когда хост попытался выполнить запись в защищенный блок либо на временно защищенную от записи, либо на постоянно защищенную от записи карту. + uint8_t card_is_locked; //Если установлен, то сигнализирует, что карта заблокирована хостом. + uint8_t lock_unlock_failed; //Устанавливается, когда была детектирована ошибка пароля в команде блокировки/разблокировки карты. + uint8_t com_crc_error; //Ошибка CRC предыдущей команды. + uint8_t illegal_command; //Команда недопустима для текущего состояния карты. + uint8_t card_ecc_failed; //Была применена внутренняя ECC, но произошла ошибка для корректных данных. + uint8_t cc_error; //Ошибка внутреннего контроллера карты. + uint8_t error; //Во время выполнения операции произошла общая или неизвестная ошибка. + uint8_t csd_overwrite; //Произошла одна из следующих ошибок: - Секция только для чтения CSD не соответствует содержимому карты. - Попытка реверса копирования (копирование в место источника), или ошибка защиты от записи. + uint8_t wp_erase_skip; //Устанавливается, когда была очищена только часть адресного пространства - из-за наличия защищенных от записи блоков, или очищалась карта, временно или постоянно защищенная от записи. + uint8_t card_ecc_disabled;//Была выполнена команда без внутреннего ECC. + uint8_t erase_reset; //Была очищена последовательность стирания перед выполнением, потому что была принята команда выхода из последовательности стирания. + uint8_t current_state; //Состояние карты, когда принимается команда. Если выполнение команды приводит к изменению состояния карты, это увидит хост в ответ на следующую команду. Эти 4 бита интерпретируются как двоичное число со значением в диапазоне от 0 до 15. + /* + 0: idle + 1: ready + 2: ident + 3: stby + 4: tran + 5: data + 6: rcv + 7: prg + 8: dis + 9..14:зарезервировано + 15: зарезервировано для режима I/O + */ + uint8_t ready_for_data; //Соответствует сигнализации по шине, что буфер пуст. + uint8_t app_cmd; //Карта ожидает ACMD, или показывается, что команда была интерпретирована как ACMD. + uint8_t ake_seq_error; //Ошибка в последовательности аутентификации. +} SD_Status_TypeDef; + + +#define SDIO_4BIT_Mode 1 +//#define SDIO_HIGH_SPEED 1 + +#define SDIO_DATA_TIMEOUT ((uint32_t)0x01000000) + +// SDIO CMD response type +#define SDIO_RESP_NONE 0x00 // No response +#define SDIO_RESP_SHORT SDIO_CMD_WAITRESP_0 // Short response +#define SDIO_RESP_LONG SDIO_CMD_WAITRESP // Long response + +// SD commands index +#define SD_CMD0 ((uint8_t)0) +#define SD_CMD8 ((uint8_t)8) +#define SD_CMD55 ((uint8_t)55) +#define SD_ACMD41 ((uint8_t)41) +#define SD_CMD2 ((uint8_t)2) +#define SD_CMD3 ((uint8_t)3) +#define SD_CMD6 ((uint8_t)6) +#define SD_CMD7 ((uint8_t)7) +#define SD_CMD9 ((uint8_t)9) + +#define SD_CMD12 ((uint8_t)12) +#define SD_CMD13 ((uint8_t)13) + +#define SD_CMD_SET_BLOCKLEN ((uint8_t)16) +#define SD_CMD_SWITCH_FUNC ((uint8_t)6U) + +#define SD_CMD17 ((uint8_t)17) +#define SD_CMD18 ((uint8_t)18) + +#define SD_CMD24 ((uint8_t)24) +#define SD_CMD25 ((uint8_t)25) + +#define SDIO_ACMD41_CHECK ((uint32_t)0x80000000) +// Pattern for R6 response +#define SD_CHECK_PATTERN ((uint32_t)0x000001AA) + +#define UM2SD (0x00) //Transfer Direction +#define SD2UM (0x02) + + + +#define DMA_S4_CLEAR ((uint32_t) DMA_IFCR_CTCIF4 | DMA_IFCR_CTEIF4 | DMA_IFCR_CGIF4 | DMA_IFCR_CHTIF4) +#define DMA_SDIO_CR ((uint32_t)( (0x03 << DMA_CCR_PL_Pos) | \ + (0x02 << DMA_CCR_MSIZE_Pos) | \ + (0x02 << DMA_CCR_PSIZE_Pos) | \ + (0x01 << DMA_CCR_MINC_Pos) | \ + (0x00 << DMA_CCR_PINC_Pos) | \ + (0x00 << DMA_CCR_CIRC_Pos)) ) + +#define SDIO_DATA_R_TIMEOUT (uint32_t)9000000 +#define SDIO_DCTRL (uint32_t)((uint32_t) 9 << SDIO_DCTRL_DBLOCKSIZE_Pos ) | ((uint32_t) 1 << SDIO_DCTRL_DMAEN_Pos) | SDIO_DCTRL_DTEN +#define SDIO_ICR_STATIC ((uint32_t)(SDIO_ICR_CCRCFAILC | SDIO_ICR_DCRCFAILC | SDIO_ICR_CTIMEOUTC | \ + SDIO_ICR_DTIMEOUTC | SDIO_ICR_TXUNDERRC | SDIO_ICR_RXOVERRC | \ + SDIO_ICR_CMDRENDC | SDIO_ICR_CMDSENTC | SDIO_ICR_DATAENDC | \ + SDIO_ICR_DBCKENDC | SDIO_ICR_STBITERRC )) + +#define SDIO_ICR_DATA_FLAGS (SDIO_ICR_DBCKENDC | SDIO_ICR_STBITERRC | SDIO_ICR_DATAENDC | SDIO_ICR_RXOVERRC | SDIO_ICR_TXUNDERRC | SDIO_ICR_DTIMEOUTC | SDIO_ICR_DCRCFAILC) +#define SDIO_ICR_CMD_FLAGS (SDIO_ICR_CEATAENDC | SDIO_ICR_SDIOITC | SDIO_ICR_CMDSENTC | SDIO_ICR_CMDRENDC | SDIO_ICR_CTIMEOUTC | SDIO_ICR_CCRCFAILC) +#define SDIO_STA_ERRORS (uint32_t)(SDIO_STA_STBITERR | SDIO_STA_RXOVERR | SDIO_STA_TXUNDERR | SDIO_STA_DTIMEOUT | SDIO_STA_DCRCFAIL ) + +#define SDIO_STA_TRX_ERROR_FLAGS (SDIO_STA_STBITERR | SDIO_STA_RXOVERR | SDIO_STA_TXUNDERR | SDIO_STA_DTIMEOUT | SDIO_STA_DCRCFAIL) +#define SDIO_STA_CMD_ERROR_FLAGS (SDIO_STA_CTIMEOUT | SDIO_STA_CCRCFAIL) +#define SDIO_STA_TRX_ACT_FLAGS (SDIO_STA_RXACT|SDIO_STA_TXACT) +#define SDIO_STA_CMD_FLAGS (uint32_t)(SDIO_STA_CCRCFAIL|SDIO_STA_CTIMEOUT|SDIO_STA_CMDSENT|SDIO_STA_CMDREND) + + +#define DISABLE_IRQ { __asm volatile ("cpsid i" : : : "memory");} +#define ENABLE_IRQ { __asm volatile ("cpsie i" : : : "memory");} + +//uint8_t SD_Init(void); +void SD_parse_CSD(uint32_t* reg); +void SD_check_status(SD_Status_TypeDef* SDStatus,uint32_t* reg); +uint32_t SD_get_block_count(void); +uint8_t SD_Cmd(uint8_t cmd, uint32_t arg, uint16_t response_type, uint32_t *response); +uint32_t SD_transfer(uint8_t *buf, uint32_t blk, uint32_t cnt, uint32_t dir); +uint8_t SD_Init(void); +//void SDIO_Config(void); + +#endif \ No newline at end of file diff --git a/Marlin/src/module/mks_wifi/mks_wifi.cpp b/Marlin/src/module/mks_wifi/mks_wifi.cpp index f09822a8cb..641a091d65 100644 --- a/Marlin/src/module/mks_wifi/mks_wifi.cpp +++ b/Marlin/src/module/mks_wifi/mks_wifi.cpp @@ -29,7 +29,10 @@ void mks_wifi_init(void){ WRITE(MKS_WIFI_IO_RST, HIGH); safe_delay(1000); WRITE(MKS_WIFI_IO4, LOW); - + // mks_wifi_sd_deinit(); + // safe_delay(100); + // mks_wifi_sd_init(); + // mks_wifi_sd_deinit(); } diff --git a/Marlin/src/module/mks_wifi/mks_wifi_sd.cpp b/Marlin/src/module/mks_wifi/mks_wifi_sd.cpp index 0dfcb729fe..23c079e00c 100644 --- a/Marlin/src/module/mks_wifi/mks_wifi_sd.cpp +++ b/Marlin/src/module/mks_wifi/mks_wifi_sd.cpp @@ -2,6 +2,7 @@ #include "../../lcd/ultralcd.h" #include "../../libs/fatfs/ff.h" +#include "../../libs/buzzer.h" FRESULT result; FATFS FATFS_Obj; @@ -16,17 +17,15 @@ volatile uint8_t __attribute__ ((aligned (4))) dma_buff2[ESP_PACKET_SIZE]; volatile uint8_t *dma_buff[] = {dma_buff1,dma_buff2}; volatile uint8_t dma_buff_index=0; volatile uint8_t *buff; -volatile uint8_t *fbuff; -volatile uint32_t dma_count; -volatile uint8_t dma_error_flag; -volatile uint8_t dma_recieve_flag; +uint8_t __attribute__ ((aligned (4))) data[DATA_SIZE]; void mks_wifi_sd_init(void){ CardReader::release(); result = f_mount((FATFS *)&FATFS_Obj, "0", 1); DEBUG("SD init %d",result); + } void mks_wifi_sd_deinit(void){ @@ -56,10 +55,7 @@ void mks_wifi_start_file_upload(ESP_PROTOC_FRAME *packet){ uint32_t dma_timeout; uint16_t data_size; FRESULT res; - uint32_t bytes_to_save; - uint8_t last_packet_flag; - uint8_t percent_done; //Установить имя файла. Смещение на 3 байта, чтобы добавить путь к диску str[0]='0'; @@ -113,57 +109,22 @@ void mks_wifi_start_file_upload(ESP_PROTOC_FRAME *packet){ DMA1->IFCR = DMA_IFCR_CGIF5|DMA_IFCR_CTEIF5|DMA_IFCR_CHTIF5|DMA_IFCR_CTCIF5; DMA1_Channel5->CCR |= DMA_CCR_EN; - //nvic_irq_enable(NVIC_DMA_CH5); file_inc_size=0; //Счетчик принятых данных, для записи в файл file_size_writen = 0; //Счетчик записанных в файл данных file_data_size = 0; dma_timeout = DMA_TIMEOUT; //Тайм-аут, на случай если передача зависла. last_sector = 0; - percent_done = 0; while(dma_timeout-- > 0){ - if(DMA1->ISR & DMA_ISR_TCIF5){ - DMA1->IFCR = DMA_IFCR_CGIF5|DMA_IFCR_CTEIF5|DMA_IFCR_CHTIF5|DMA_IFCR_CTCIF5; - //переключить индекс - dma_buff_index++; - if(dma_buff_index == DMA_BUFF_COUNT){ - WRITE(MKS_WIFI_IO4, HIGH); - dma_recieve_flag=1; - }else{ - DMA1_Channel5->CCR = DMA_CCR_PL|DMA_CCR_MINC; - DMA1_Channel5->CPAR = (uint32_t)&USART1->DR; - DMA1_Channel5->CMAR = (uint32_t)dma_buff[dma_buff_index]; - DMA1_Channel5->CNDTR = ESP_PACKET_SIZE; - DMA1_Channel5->CCR |= DMA_CCR_EN; - } - } - - if(DMA1->ISR & DMA_ISR_TEIF5){ - dma_error_flag=1; - } - - - - if(dma_recieve_flag){ - memset((uint8_t*)file_buff,0,DMA_BUFF_COUNT*ESP_PACKET_SIZE); - bytes_to_save=0; - fbuff = file_buff; - for(uint32_t i=0; iISR & DMA_ISR_TCIF5){ + DMA1->IFCR = DMA_IFCR_CGIF5|DMA_IFCR_CTEIF5|DMA_IFCR_CHTIF5|DMA_IFCR_CTCIF5; + + //Указатель на полученный буфер + buff=dma_buff[dma_buff_index]; + //переключить индекс + dma_buff_index = (dma_buff_index) ? 0 : 1; //Запустить DMA на прием следующего пакета, пока обрабатывается этот DMA1_Channel5->CCR = DMA_CCR_PL|DMA_CCR_MINC; @@ -202,14 +163,16 @@ void mks_wifi_start_file_upload(ESP_PROTOC_FRAME *packet){ break; } file_size_writen+=bytes_writen; - f_sync((FIL *)&upload_file); - - if((percent_done+5) == (uint8_t)(file_inc_size*100/file_size) ){ //Отображать прогресс только при изменении - percent_done = file_inc_size*100/file_size; - sprintf(str,"Upload %ld%%",file_inc_size*100/file_size); - ui.set_status((const char *)str,true); - ui.update(); + res=f_sync((FIL *)&upload_file); + if(res){ + ERROR("Fsync err %d",res); + break; } + + + sprintf(str,"Upload %ld%%",file_inc_size*100/file_size); + ui.set_status((const char *)str,true); + ui.update(); memset((uint8_t *)file_buff,0,(ESP_FILE_BUFF_COUNT*ESP_PACKET_SIZE)); file_data_size=0; @@ -260,9 +223,15 @@ void mks_wifi_start_file_upload(ESP_PROTOC_FRAME *packet){ if( (file_size == file_inc_size) && (file_size == file_size_writen) ){ ui.set_status((const char *)"Upload done",true); DEBUG("Upload ok"); + BUZZ(1000,260); }else{ ui.set_status((const char *)"Upload failed",true); DEBUG("Upload failed! File size: %d; Recieve %d; SD write %d",file_size,file_inc_size,file_size_writen); + BUZZ(436,392); + BUZZ(109,0); + BUZZ(436,392); + BUZZ(109,0); + BUZZ(436,392); } //Восстановить USART1 @@ -282,30 +251,3 @@ void mks_wifi_start_file_upload(ESP_PROTOC_FRAME *packet){ DEBUG("Settings restored"); } -/* -void __irq_dma1_channel5(void) { - if(DMA1->ISR & DMA_ISR_TCIF5){ - DMA1->IFCR = DMA_IFCR_CGIF5|DMA_IFCR_CTEIF5|DMA_IFCR_CHTIF5|DMA_IFCR_CTCIF5; - - //переключить индекс - dma_buff_index++; - - if(dma_buff_index == DMA_BUFF_COUNT){ - WRITE(MKS_WIFI_IO4, HIGH); - dma_recieve_flag=1; - return; - } - - DMA1_Channel5->CCR = DMA_CCR_PL|DMA_CCR_MINC; - DMA1_Channel5->CPAR = (uint32_t)&USART1->DR; - DMA1_Channel5->CMAR = (uint32_t)dma_buff[dma_buff_index]; - DMA1_Channel5->CNDTR = ESP_PACKET_SIZE; - DMA1_Channel5->CCR |= DMA_CCR_EN; - } - - if(DMA1->ISR & DMA_ISR_TEIF5){ - dma_error_flag=1; - } - -} -*/ \ No newline at end of file diff --git a/Marlin/src/module/mks_wifi/mks_wifi_sd.h b/Marlin/src/module/mks_wifi/mks_wifi_sd.h index a6976dd6d2..0de75b6fc5 100644 --- a/Marlin/src/module/mks_wifi/mks_wifi_sd.h +++ b/Marlin/src/module/mks_wifi/mks_wifi_sd.h @@ -1,17 +1,19 @@ #ifndef MKS_WIFI_SD_H #define MKS_WIFI_SD_H -#define DMA_TIMEOUT 0xffffff +#define DMA_TIMEOUT 0xFffffff #include "mks_wifi.h" #include "../../sd/cardreader.h" #include "small_cmsis.h" -#define DMA_BUFF_COUNT 2 -#define DMA_BUFF_SIZE 1024 #define ESP_PACKET_SIZE 1024 -#define ESP_FILE_BUFF_COUNT 4 +#define ESP_FILE_BUFF_COUNT 8 + +#define DATA_SIZE 16*1024 +#define WRITE_COUNT 255 + void mks_wifi_sd_init(void); void mks_wifi_sd_deinit(void); @@ -19,6 +21,4 @@ void sd_delete_file(char *filename); void mks_wifi_start_file_upload(ESP_PROTOC_FRAME *packet); -void __irq_dma1_channel5(void); - #endif \ No newline at end of file diff --git a/Marlin/src/module/mks_wifi/mks_wifi_sd_low_lev.cpp b/Marlin/src/module/mks_wifi/mks_wifi_sd_low_lev.cpp index 5ec35c2e1c..d9ba67fdb4 100644 --- a/Marlin/src/module/mks_wifi/mks_wifi_sd_low_lev.cpp +++ b/Marlin/src/module/mks_wifi/mks_wifi_sd_low_lev.cpp @@ -1,8 +1,11 @@ +/* #include "mks_wifi_sd_low_lev.h" #include "../../sd/Sd2Card_sdio.h" +#include "../../HAL/STM32F1/sdio.h" +//volatile uint8_t __attribute__ ((aligned (4))) align_buff[512]; -volatile uint8_t __attribute__ ((aligned (4))) align_buff[512]; +extern SDIO_CardInfoTypeDef SdCard; uint8_t sd_init(void){ @@ -13,6 +16,10 @@ uint8_t sd_init(void){ } } +uint32_t sd_get_rca(void){ + return SdCard.RelCardAdd; +} + uint8_t sd_read(uint8_t *buf, uint32_t sector,uint32_t count){ uint8_t res; @@ -63,4 +70,5 @@ uint8_t sd_write(uint8_t *buf, uint32_t sector,uint32_t count){ } } return 0; -} \ No newline at end of file +} +*/ \ No newline at end of file diff --git a/Marlin/src/module/mks_wifi/mks_wifi_sd_low_lev.h b/Marlin/src/module/mks_wifi/mks_wifi_sd_low_lev.h index 4fe84d31f8..ba6613ef3b 100644 --- a/Marlin/src/module/mks_wifi/mks_wifi_sd_low_lev.h +++ b/Marlin/src/module/mks_wifi/mks_wifi_sd_low_lev.h @@ -1,3 +1,4 @@ +/* #ifndef MKS_WIFI_SD_LL_H #define MKS_WIFI_SD_LL_H @@ -7,5 +8,8 @@ uint8_t sd_init(void); uint8_t sd_read(uint8_t *buf, uint32_t sector,uint32_t count); uint8_t sd_write(uint8_t *buf, uint32_t sector,uint32_t count); +uint32_t sd_get_rca(void); #endif + +*/ diff --git a/Marlin/src/module/mks_wifi/mks_wifi_settings.h b/Marlin/src/module/mks_wifi/mks_wifi_settings.h index 4b9a90a9e9..7e6927efb3 100644 --- a/Marlin/src/module/mks_wifi/mks_wifi_settings.h +++ b/Marlin/src/module/mks_wifi/mks_wifi_settings.h @@ -4,4 +4,8 @@ #define MKS_WIFI_SSID "MikroTik2" #define MKS_WIFI_KEY "vg3Apswqvg3Aps" +//#define MKS_WIFI_SSID "Dlink602_1" +//#define MKS_WIFI_KEY "Hnt45vh4JySqi" + + #endif diff --git a/Marlin/src/module/mks_wifi/small_cmsis.h b/Marlin/src/module/mks_wifi/small_cmsis.h index 04029af01d..7c6c0c6cb0 100644 --- a/Marlin/src/module/mks_wifi/small_cmsis.h +++ b/Marlin/src/module/mks_wifi/small_cmsis.h @@ -4,6 +4,7 @@ #include "mks_wifi.h" #define __IO volatile /*!< Defines 'read / write' permissions */ +#define __I volatile const /*!< Defines 'read only' permissions */ typedef struct { @@ -30,6 +31,46 @@ typedef struct __IO uint32_t CMAR; } DMA_Channel_TypeDef; +typedef struct +{ + __IO uint32_t POWER; + __IO uint32_t CLKCR; + __IO uint32_t ARG; + __IO uint32_t CMD; + __I uint32_t RESPCMD; + __I uint32_t RESP1; + __I uint32_t RESP2; + __I uint32_t RESP3; + __I uint32_t RESP4; + __IO uint32_t DTIMER; + __IO uint32_t DLEN; + __IO uint32_t DCTRL; + __I uint32_t DCOUNT; + __I uint32_t STA; + __IO uint32_t ICR; + __IO uint32_t MASK; + uint32_t RESERVED0[2]; + __I uint32_t FIFOCNT; + uint32_t RESERVED1[13]; + __IO uint32_t FIFO; +} SDIO_TypeDef; + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t CFGR; + __IO uint32_t CIR; + __IO uint32_t APB2RSTR; + __IO uint32_t APB1RSTR; + __IO uint32_t AHBENR; + __IO uint32_t APB2ENR; + __IO uint32_t APB1ENR; + __IO uint32_t BDCR; + __IO uint32_t CSR; + + +} RCC_TypeDef; + #define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */ #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U) @@ -37,13 +78,18 @@ typedef struct #define USART1_BASE (APB2PERIPH_BASE + 0x00003800U) #define DMA1_BASE (AHBPERIPH_BASE + 0x00000000U) #define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x00000058U) - - -#define USART1 ((USART_TypeDef *)USART1_BASE) -#define DMA1 ((DMA_TypeDef *)DMA1_BASE) - -#define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE) - +#define DMA2_BASE (AHBPERIPH_BASE + 0x00000400U) +#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x00000444U) +#define SDIO_BASE (PERIPH_BASE + 0x00018000U) +//#define RCC_BASE (AHBPERIPH_BASE + 0x00001000U) + +#define RCC ((RCC_TypeDef *)RCC_BASE) +#define SDIO ((SDIO_TypeDef *)SDIO_BASE) +#define USART1 ((USART_TypeDef *)USART1_BASE) +#define DMA1 ((DMA_TypeDef *)DMA1_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE) +#define DMA2_Channel4 ((DMA_Channel_TypeDef *)DMA2_Channel4_BASE) +#define DMA2 ((DMA_TypeDef *)DMA2_BASE) /******************************************************************************/ /* */ @@ -468,4 +514,361 @@ typedef struct #define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */ +/******************************************************************************/ +/* */ +/* SD host Interface */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for SDIO_POWER register ******************/ +#define SDIO_POWER_PWRCTRL_Pos (0U) +#define SDIO_POWER_PWRCTRL_Msk (0x3U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x00000003 */ +#define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk /*!< PWRCTRL[1:0] bits (Power supply control bits) */ +#define SDIO_POWER_PWRCTRL_0 (0x1U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x01 */ +#define SDIO_POWER_PWRCTRL_1 (0x2U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x02 */ + +/****************** Bit definition for SDIO_CLKCR register ******************/ +#define SDIO_CLKCR_CLKDIV_Pos (0U) +#define SDIO_CLKCR_CLKDIV_Msk (0xFFU << SDIO_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */ +#define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk /*!< Clock divide factor */ +#define SDIO_CLKCR_CLKEN_Pos (8U) +#define SDIO_CLKCR_CLKEN_Msk (0x1U << SDIO_CLKCR_CLKEN_Pos) /*!< 0x00000100 */ +#define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk /*!< Clock enable bit */ +#define SDIO_CLKCR_PWRSAV_Pos (9U) +#define SDIO_CLKCR_PWRSAV_Msk (0x1U << SDIO_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */ +#define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk /*!< Power saving configuration bit */ +#define SDIO_CLKCR_BYPASS_Pos (10U) +#define SDIO_CLKCR_BYPASS_Msk (0x1U << SDIO_CLKCR_BYPASS_Pos) /*!< 0x00000400 */ +#define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk /*!< Clock divider bypass enable bit */ + +#define SDIO_CLKCR_WIDBUS_Pos (11U) +#define SDIO_CLKCR_WIDBUS_Msk (0x3U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */ +#define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk /*!< WIDBUS[1:0] bits (Wide bus mode enable bit) */ +#define SDIO_CLKCR_WIDBUS_0 (0x1U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x0800 */ +#define SDIO_CLKCR_WIDBUS_1 (0x2U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x1000 */ + +#define SDIO_CLKCR_NEGEDGE_Pos (13U) +#define SDIO_CLKCR_NEGEDGE_Msk (0x1U << SDIO_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */ +#define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk /*!< SDIO_CK dephasing selection bit */ +#define SDIO_CLKCR_HWFC_EN_Pos (14U) +#define SDIO_CLKCR_HWFC_EN_Msk (0x1U << SDIO_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */ +#define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk /*!< HW Flow Control enable */ + +/******************* Bit definition for SDIO_ARG register *******************/ +#define SDIO_ARG_CMDARG_Pos (0U) +#define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFU << SDIO_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */ +#define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk /*!< Command argument */ + +/******************* Bit definition for SDIO_CMD register *******************/ +#define SDIO_CMD_CMDINDEX_Pos (0U) +#define SDIO_CMD_CMDINDEX_Msk (0x3FU << SDIO_CMD_CMDINDEX_Pos) /*!< 0x0000003F */ +#define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk /*!< Command Index */ + +#define SDIO_CMD_WAITRESP_Pos (6U) +#define SDIO_CMD_WAITRESP_Msk (0x3U << SDIO_CMD_WAITRESP_Pos) /*!< 0x000000C0 */ +#define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk /*!< WAITRESP[1:0] bits (Wait for response bits) */ +#define SDIO_CMD_WAITRESP_0 (0x1U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0040 */ +#define SDIO_CMD_WAITRESP_1 (0x2U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0080 */ + +#define SDIO_CMD_WAITINT_Pos (8U) +#define SDIO_CMD_WAITINT_Msk (0x1U << SDIO_CMD_WAITINT_Pos) /*!< 0x00000100 */ +#define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk /*!< CPSM Waits for Interrupt Request */ +#define SDIO_CMD_WAITPEND_Pos (9U) +#define SDIO_CMD_WAITPEND_Msk (0x1U << SDIO_CMD_WAITPEND_Pos) /*!< 0x00000200 */ +#define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk /*!< CPSM Waits for ends of data transfer (CmdPend internal signal) */ +#define SDIO_CMD_CPSMEN_Pos (10U) +#define SDIO_CMD_CPSMEN_Msk (0x1U << SDIO_CMD_CPSMEN_Pos) /*!< 0x00000400 */ +#define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk /*!< Command path state machine (CPSM) Enable bit */ +#define SDIO_CMD_SDIOSUSPEND_Pos (11U) +#define SDIO_CMD_SDIOSUSPEND_Msk (0x1U << SDIO_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */ +#define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk /*!< SD I/O suspend command */ +#define SDIO_CMD_ENCMDCOMPL_Pos (12U) +#define SDIO_CMD_ENCMDCOMPL_Msk (0x1U << SDIO_CMD_ENCMDCOMPL_Pos) /*!< 0x00001000 */ +#define SDIO_CMD_ENCMDCOMPL SDIO_CMD_ENCMDCOMPL_Msk /*!< Enable CMD completion */ +#define SDIO_CMD_NIEN_Pos (13U) +#define SDIO_CMD_NIEN_Msk (0x1U << SDIO_CMD_NIEN_Pos) /*!< 0x00002000 */ +#define SDIO_CMD_NIEN SDIO_CMD_NIEN_Msk /*!< Not Interrupt Enable */ +#define SDIO_CMD_CEATACMD_Pos (14U) +#define SDIO_CMD_CEATACMD_Msk (0x1U << SDIO_CMD_CEATACMD_Pos) /*!< 0x00004000 */ +#define SDIO_CMD_CEATACMD SDIO_CMD_CEATACMD_Msk /*!< CE-ATA command */ + +/***************** Bit definition for SDIO_RESPCMD register *****************/ +#define SDIO_RESPCMD_RESPCMD_Pos (0U) +#define SDIO_RESPCMD_RESPCMD_Msk (0x3FU << SDIO_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */ +#define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk /*!< Response command index */ + +/****************** Bit definition for SDIO_RESP0 register ******************/ +#define SDIO_RESP0_CARDSTATUS0_Pos (0U) +#define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFU << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */ +#define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk /*!< Card Status */ + +/****************** Bit definition for SDIO_RESP1 register ******************/ +#define SDIO_RESP1_CARDSTATUS1_Pos (0U) +#define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFU << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */ +#define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk /*!< Card Status */ + +/****************** Bit definition for SDIO_RESP2 register ******************/ +#define SDIO_RESP2_CARDSTATUS2_Pos (0U) +#define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFU << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */ +#define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk /*!< Card Status */ + +/****************** Bit definition for SDIO_RESP3 register ******************/ +#define SDIO_RESP3_CARDSTATUS3_Pos (0U) +#define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFU << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */ +#define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk /*!< Card Status */ + +/****************** Bit definition for SDIO_RESP4 register ******************/ +#define SDIO_RESP4_CARDSTATUS4_Pos (0U) +#define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFU << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */ +#define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk /*!< Card Status */ + +/****************** Bit definition for SDIO_DTIMER register *****************/ +#define SDIO_DTIMER_DATATIME_Pos (0U) +#define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFU << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */ +#define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk /*!< Data timeout period. */ + +/****************** Bit definition for SDIO_DLEN register *******************/ +#define SDIO_DLEN_DATALENGTH_Pos (0U) +#define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFU << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */ +#define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk /*!< Data length value */ + +/****************** Bit definition for SDIO_DCTRL register ******************/ +#define SDIO_DCTRL_DTEN_Pos (0U) +#define SDIO_DCTRL_DTEN_Msk (0x1U << SDIO_DCTRL_DTEN_Pos) /*!< 0x00000001 */ +#define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk /*!< Data transfer enabled bit */ +#define SDIO_DCTRL_DTDIR_Pos (1U) +#define SDIO_DCTRL_DTDIR_Msk (0x1U << SDIO_DCTRL_DTDIR_Pos) /*!< 0x00000002 */ +#define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk /*!< Data transfer direction selection */ +#define SDIO_DCTRL_DTMODE_Pos (2U) +#define SDIO_DCTRL_DTMODE_Msk (0x1U << SDIO_DCTRL_DTMODE_Pos) /*!< 0x00000004 */ +#define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk /*!< Data transfer mode selection */ +#define SDIO_DCTRL_DMAEN_Pos (3U) +#define SDIO_DCTRL_DMAEN_Msk (0x1U << SDIO_DCTRL_DMAEN_Pos) /*!< 0x00000008 */ +#define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk /*!< DMA enabled bit */ + +#define SDIO_DCTRL_DBLOCKSIZE_Pos (4U) +#define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFU << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */ +#define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk /*!< DBLOCKSIZE[3:0] bits (Data block size) */ +#define SDIO_DCTRL_DBLOCKSIZE_0 (0x1U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0010 */ +#define SDIO_DCTRL_DBLOCKSIZE_1 (0x2U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0020 */ +#define SDIO_DCTRL_DBLOCKSIZE_2 (0x4U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0040 */ +#define SDIO_DCTRL_DBLOCKSIZE_3 (0x8U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0080 */ + +#define SDIO_DCTRL_RWSTART_Pos (8U) +#define SDIO_DCTRL_RWSTART_Msk (0x1U << SDIO_DCTRL_RWSTART_Pos) /*!< 0x00000100 */ +#define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk /*!< Read wait start */ +#define SDIO_DCTRL_RWSTOP_Pos (9U) +#define SDIO_DCTRL_RWSTOP_Msk (0x1U << SDIO_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */ +#define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk /*!< Read wait stop */ +#define SDIO_DCTRL_RWMOD_Pos (10U) +#define SDIO_DCTRL_RWMOD_Msk (0x1U << SDIO_DCTRL_RWMOD_Pos) /*!< 0x00000400 */ +#define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk /*!< Read wait mode */ +#define SDIO_DCTRL_SDIOEN_Pos (11U) +#define SDIO_DCTRL_SDIOEN_Msk (0x1U << SDIO_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */ +#define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk /*!< SD I/O enable functions */ + +/****************** Bit definition for SDIO_DCOUNT register *****************/ +#define SDIO_DCOUNT_DATACOUNT_Pos (0U) +#define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFU << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */ +#define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk /*!< Data count value */ + +/****************** Bit definition for SDIO_STA register ********************/ +#define SDIO_STA_CCRCFAIL_Pos (0U) +#define SDIO_STA_CCRCFAIL_Msk (0x1U << SDIO_STA_CCRCFAIL_Pos) /*!< 0x00000001 */ +#define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk /*!< Command response received (CRC check failed) */ +#define SDIO_STA_DCRCFAIL_Pos (1U) +#define SDIO_STA_DCRCFAIL_Msk (0x1U << SDIO_STA_DCRCFAIL_Pos) /*!< 0x00000002 */ +#define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk /*!< Data block sent/received (CRC check failed) */ +#define SDIO_STA_CTIMEOUT_Pos (2U) +#define SDIO_STA_CTIMEOUT_Msk (0x1U << SDIO_STA_CTIMEOUT_Pos) /*!< 0x00000004 */ +#define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk /*!< Command response timeout */ +#define SDIO_STA_DTIMEOUT_Pos (3U) +#define SDIO_STA_DTIMEOUT_Msk (0x1U << SDIO_STA_DTIMEOUT_Pos) /*!< 0x00000008 */ +#define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk /*!< Data timeout */ +#define SDIO_STA_TXUNDERR_Pos (4U) +#define SDIO_STA_TXUNDERR_Msk (0x1U << SDIO_STA_TXUNDERR_Pos) /*!< 0x00000010 */ +#define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk /*!< Transmit FIFO underrun error */ +#define SDIO_STA_RXOVERR_Pos (5U) +#define SDIO_STA_RXOVERR_Msk (0x1U << SDIO_STA_RXOVERR_Pos) /*!< 0x00000020 */ +#define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk /*!< Received FIFO overrun error */ +#define SDIO_STA_CMDREND_Pos (6U) +#define SDIO_STA_CMDREND_Msk (0x1U << SDIO_STA_CMDREND_Pos) /*!< 0x00000040 */ +#define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk /*!< Command response received (CRC check passed) */ +#define SDIO_STA_CMDSENT_Pos (7U) +#define SDIO_STA_CMDSENT_Msk (0x1U << SDIO_STA_CMDSENT_Pos) /*!< 0x00000080 */ +#define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk /*!< Command sent (no response required) */ +#define SDIO_STA_DATAEND_Pos (8U) +#define SDIO_STA_DATAEND_Msk (0x1U << SDIO_STA_DATAEND_Pos) /*!< 0x00000100 */ +#define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk /*!< Data end (data counter, SDIDCOUNT, is zero) */ +#define SDIO_STA_STBITERR_Pos (9U) +#define SDIO_STA_STBITERR_Msk (0x1U << SDIO_STA_STBITERR_Pos) /*!< 0x00000200 */ +#define SDIO_STA_STBITERR SDIO_STA_STBITERR_Msk /*!< Start bit not detected on all data signals in wide bus mode */ +#define SDIO_STA_DBCKEND_Pos (10U) +#define SDIO_STA_DBCKEND_Msk (0x1U << SDIO_STA_DBCKEND_Pos) /*!< 0x00000400 */ +#define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk /*!< Data block sent/received (CRC check passed) */ +#define SDIO_STA_CMDACT_Pos (11U) +#define SDIO_STA_CMDACT_Msk (0x1U << SDIO_STA_CMDACT_Pos) /*!< 0x00000800 */ +#define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk /*!< Command transfer in progress */ +#define SDIO_STA_TXACT_Pos (12U) +#define SDIO_STA_TXACT_Msk (0x1U << SDIO_STA_TXACT_Pos) /*!< 0x00001000 */ +#define SDIO_STA_TXACT SDIO_STA_TXACT_Msk /*!< Data transmit in progress */ +#define SDIO_STA_RXACT_Pos (13U) +#define SDIO_STA_RXACT_Msk (0x1U << SDIO_STA_RXACT_Pos) /*!< 0x00002000 */ +#define SDIO_STA_RXACT SDIO_STA_RXACT_Msk /*!< Data receive in progress */ +#define SDIO_STA_TXFIFOHE_Pos (14U) +#define SDIO_STA_TXFIFOHE_Msk (0x1U << SDIO_STA_TXFIFOHE_Pos) /*!< 0x00004000 */ +#define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk /*!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */ +#define SDIO_STA_RXFIFOHF_Pos (15U) +#define SDIO_STA_RXFIFOHF_Msk (0x1U << SDIO_STA_RXFIFOHF_Pos) /*!< 0x00008000 */ +#define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk /*!< Receive FIFO Half Full: there are at least 8 words in the FIFO */ +#define SDIO_STA_TXFIFOF_Pos (16U) +#define SDIO_STA_TXFIFOF_Msk (0x1U << SDIO_STA_TXFIFOF_Pos) /*!< 0x00010000 */ +#define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk /*!< Transmit FIFO full */ +#define SDIO_STA_RXFIFOF_Pos (17U) +#define SDIO_STA_RXFIFOF_Msk (0x1U << SDIO_STA_RXFIFOF_Pos) /*!< 0x00020000 */ +#define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk /*!< Receive FIFO full */ +#define SDIO_STA_TXFIFOE_Pos (18U) +#define SDIO_STA_TXFIFOE_Msk (0x1U << SDIO_STA_TXFIFOE_Pos) /*!< 0x00040000 */ +#define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk /*!< Transmit FIFO empty */ +#define SDIO_STA_RXFIFOE_Pos (19U) +#define SDIO_STA_RXFIFOE_Msk (0x1U << SDIO_STA_RXFIFOE_Pos) /*!< 0x00080000 */ +#define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk /*!< Receive FIFO empty */ +#define SDIO_STA_TXDAVL_Pos (20U) +#define SDIO_STA_TXDAVL_Msk (0x1U << SDIO_STA_TXDAVL_Pos) /*!< 0x00100000 */ +#define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk /*!< Data available in transmit FIFO */ +#define SDIO_STA_RXDAVL_Pos (21U) +#define SDIO_STA_RXDAVL_Msk (0x1U << SDIO_STA_RXDAVL_Pos) /*!< 0x00200000 */ +#define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk /*!< Data available in receive FIFO */ +#define SDIO_STA_SDIOIT_Pos (22U) +#define SDIO_STA_SDIOIT_Msk (0x1U << SDIO_STA_SDIOIT_Pos) /*!< 0x00400000 */ +#define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk /*!< SDIO interrupt received */ +#define SDIO_STA_CEATAEND_Pos (23U) +#define SDIO_STA_CEATAEND_Msk (0x1U << SDIO_STA_CEATAEND_Pos) /*!< 0x00800000 */ +#define SDIO_STA_CEATAEND SDIO_STA_CEATAEND_Msk /*!< CE-ATA command completion signal received for CMD61 */ + +/******************* Bit definition for SDIO_ICR register *******************/ +#define SDIO_ICR_CCRCFAILC_Pos (0U) +#define SDIO_ICR_CCRCFAILC_Msk (0x1U << SDIO_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */ +#define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk /*!< CCRCFAIL flag clear bit */ +#define SDIO_ICR_DCRCFAILC_Pos (1U) +#define SDIO_ICR_DCRCFAILC_Msk (0x1U << SDIO_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */ +#define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk /*!< DCRCFAIL flag clear bit */ +#define SDIO_ICR_CTIMEOUTC_Pos (2U) +#define SDIO_ICR_CTIMEOUTC_Msk (0x1U << SDIO_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */ +#define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk /*!< CTIMEOUT flag clear bit */ +#define SDIO_ICR_DTIMEOUTC_Pos (3U) +#define SDIO_ICR_DTIMEOUTC_Msk (0x1U << SDIO_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */ +#define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk /*!< DTIMEOUT flag clear bit */ +#define SDIO_ICR_TXUNDERRC_Pos (4U) +#define SDIO_ICR_TXUNDERRC_Msk (0x1U << SDIO_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */ +#define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk /*!< TXUNDERR flag clear bit */ +#define SDIO_ICR_RXOVERRC_Pos (5U) +#define SDIO_ICR_RXOVERRC_Msk (0x1U << SDIO_ICR_RXOVERRC_Pos) /*!< 0x00000020 */ +#define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk /*!< RXOVERR flag clear bit */ +#define SDIO_ICR_CMDRENDC_Pos (6U) +#define SDIO_ICR_CMDRENDC_Msk (0x1U << SDIO_ICR_CMDRENDC_Pos) /*!< 0x00000040 */ +#define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk /*!< CMDREND flag clear bit */ +#define SDIO_ICR_CMDSENTC_Pos (7U) +#define SDIO_ICR_CMDSENTC_Msk (0x1U << SDIO_ICR_CMDSENTC_Pos) /*!< 0x00000080 */ +#define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk /*!< CMDSENT flag clear bit */ +#define SDIO_ICR_DATAENDC_Pos (8U) +#define SDIO_ICR_DATAENDC_Msk (0x1U << SDIO_ICR_DATAENDC_Pos) /*!< 0x00000100 */ +#define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk /*!< DATAEND flag clear bit */ +#define SDIO_ICR_STBITERRC_Pos (9U) +#define SDIO_ICR_STBITERRC_Msk (0x1U << SDIO_ICR_STBITERRC_Pos) /*!< 0x00000200 */ +#define SDIO_ICR_STBITERRC SDIO_ICR_STBITERRC_Msk /*!< STBITERR flag clear bit */ +#define SDIO_ICR_DBCKENDC_Pos (10U) +#define SDIO_ICR_DBCKENDC_Msk (0x1U << SDIO_ICR_DBCKENDC_Pos) /*!< 0x00000400 */ +#define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk /*!< DBCKEND flag clear bit */ +#define SDIO_ICR_SDIOITC_Pos (22U) +#define SDIO_ICR_SDIOITC_Msk (0x1U << SDIO_ICR_SDIOITC_Pos) /*!< 0x00400000 */ +#define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk /*!< SDIOIT flag clear bit */ +#define SDIO_ICR_CEATAENDC_Pos (23U) +#define SDIO_ICR_CEATAENDC_Msk (0x1U << SDIO_ICR_CEATAENDC_Pos) /*!< 0x00800000 */ +#define SDIO_ICR_CEATAENDC SDIO_ICR_CEATAENDC_Msk /*!< CEATAEND flag clear bit */ + +/****************** Bit definition for SDIO_MASK register *******************/ +#define SDIO_MASK_CCRCFAILIE_Pos (0U) +#define SDIO_MASK_CCRCFAILIE_Msk (0x1U << SDIO_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */ +#define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk /*!< Command CRC Fail Interrupt Enable */ +#define SDIO_MASK_DCRCFAILIE_Pos (1U) +#define SDIO_MASK_DCRCFAILIE_Msk (0x1U << SDIO_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */ +#define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk /*!< Data CRC Fail Interrupt Enable */ +#define SDIO_MASK_CTIMEOUTIE_Pos (2U) +#define SDIO_MASK_CTIMEOUTIE_Msk (0x1U << SDIO_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */ +#define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk /*!< Command TimeOut Interrupt Enable */ +#define SDIO_MASK_DTIMEOUTIE_Pos (3U) +#define SDIO_MASK_DTIMEOUTIE_Msk (0x1U << SDIO_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */ +#define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk /*!< Data TimeOut Interrupt Enable */ +#define SDIO_MASK_TXUNDERRIE_Pos (4U) +#define SDIO_MASK_TXUNDERRIE_Msk (0x1U << SDIO_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */ +#define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk /*!< Tx FIFO UnderRun Error Interrupt Enable */ +#define SDIO_MASK_RXOVERRIE_Pos (5U) +#define SDIO_MASK_RXOVERRIE_Msk (0x1U << SDIO_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */ +#define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk /*!< Rx FIFO OverRun Error Interrupt Enable */ +#define SDIO_MASK_CMDRENDIE_Pos (6U) +#define SDIO_MASK_CMDRENDIE_Msk (0x1U << SDIO_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */ +#define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk /*!< Command Response Received Interrupt Enable */ +#define SDIO_MASK_CMDSENTIE_Pos (7U) +#define SDIO_MASK_CMDSENTIE_Msk (0x1U << SDIO_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */ +#define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk /*!< Command Sent Interrupt Enable */ +#define SDIO_MASK_DATAENDIE_Pos (8U) +#define SDIO_MASK_DATAENDIE_Msk (0x1U << SDIO_MASK_DATAENDIE_Pos) /*!< 0x00000100 */ +#define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk /*!< Data End Interrupt Enable */ +#define SDIO_MASK_STBITERRIE_Pos (9U) +#define SDIO_MASK_STBITERRIE_Msk (0x1U << SDIO_MASK_STBITERRIE_Pos) /*!< 0x00000200 */ +#define SDIO_MASK_STBITERRIE SDIO_MASK_STBITERRIE_Msk /*!< Start Bit Error Interrupt Enable */ +#define SDIO_MASK_DBCKENDIE_Pos (10U) +#define SDIO_MASK_DBCKENDIE_Msk (0x1U << SDIO_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */ +#define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk /*!< Data Block End Interrupt Enable */ +#define SDIO_MASK_CMDACTIE_Pos (11U) +#define SDIO_MASK_CMDACTIE_Msk (0x1U << SDIO_MASK_CMDACTIE_Pos) /*!< 0x00000800 */ +#define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk /*!< Command Acting Interrupt Enable */ +#define SDIO_MASK_TXACTIE_Pos (12U) +#define SDIO_MASK_TXACTIE_Msk (0x1U << SDIO_MASK_TXACTIE_Pos) /*!< 0x00001000 */ +#define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk /*!< Data Transmit Acting Interrupt Enable */ +#define SDIO_MASK_RXACTIE_Pos (13U) +#define SDIO_MASK_RXACTIE_Msk (0x1U << SDIO_MASK_RXACTIE_Pos) /*!< 0x00002000 */ +#define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk /*!< Data receive acting interrupt enabled */ +#define SDIO_MASK_TXFIFOHEIE_Pos (14U) +#define SDIO_MASK_TXFIFOHEIE_Msk (0x1U << SDIO_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */ +#define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk /*!< Tx FIFO Half Empty interrupt Enable */ +#define SDIO_MASK_RXFIFOHFIE_Pos (15U) +#define SDIO_MASK_RXFIFOHFIE_Msk (0x1U << SDIO_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */ +#define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk /*!< Rx FIFO Half Full interrupt Enable */ +#define SDIO_MASK_TXFIFOFIE_Pos (16U) +#define SDIO_MASK_TXFIFOFIE_Msk (0x1U << SDIO_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */ +#define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk /*!< Tx FIFO Full interrupt Enable */ +#define SDIO_MASK_RXFIFOFIE_Pos (17U) +#define SDIO_MASK_RXFIFOFIE_Msk (0x1U << SDIO_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */ +#define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk /*!< Rx FIFO Full interrupt Enable */ +#define SDIO_MASK_TXFIFOEIE_Pos (18U) +#define SDIO_MASK_TXFIFOEIE_Msk (0x1U << SDIO_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */ +#define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk /*!< Tx FIFO Empty interrupt Enable */ +#define SDIO_MASK_RXFIFOEIE_Pos (19U) +#define SDIO_MASK_RXFIFOEIE_Msk (0x1U << SDIO_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */ +#define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk /*!< Rx FIFO Empty interrupt Enable */ +#define SDIO_MASK_TXDAVLIE_Pos (20U) +#define SDIO_MASK_TXDAVLIE_Msk (0x1U << SDIO_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */ +#define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk /*!< Data available in Tx FIFO interrupt Enable */ +#define SDIO_MASK_RXDAVLIE_Pos (21U) +#define SDIO_MASK_RXDAVLIE_Msk (0x1U << SDIO_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */ +#define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk /*!< Data available in Rx FIFO interrupt Enable */ +#define SDIO_MASK_SDIOITIE_Pos (22U) +#define SDIO_MASK_SDIOITIE_Msk (0x1U << SDIO_MASK_SDIOITIE_Pos) /*!< 0x00400000 */ +#define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk /*!< SDIO Mode Interrupt Received interrupt Enable */ +#define SDIO_MASK_CEATAENDIE_Pos (23U) +#define SDIO_MASK_CEATAENDIE_Msk (0x1U << SDIO_MASK_CEATAENDIE_Pos) /*!< 0x00800000 */ +#define SDIO_MASK_CEATAENDIE SDIO_MASK_CEATAENDIE_Msk /*!< CE-ATA command completion signal received Interrupt Enable */ + +/***************** Bit definition for SDIO_FIFOCNT register *****************/ +#define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U) +#define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFU << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */ +#define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk /*!< Remaining number of words to be written to or read from the FIFO */ + +/****************** Bit definition for SDIO_FIFO register *******************/ +#define SDIO_FIFO_FIFODATA_Pos (0U) +#define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFU << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */ +#define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk /*!< Receive and transmit FIFO data */ + #endif \ No newline at end of file