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Spacing, macros in LPC1768_PWM

pull/1/head
Scott Lahteine 7 years ago
parent
a67cf78c6b
commit
c8718aa111
1 changed files with 54 additions and 52 deletions
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  1. 22
      Marlin/src/HAL/HAL_LPC1768/LPC1768_PWM.cpp

22
Marlin/src/HAL/HAL_LPC1768/LPC1768_PWM.cpp
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@ -153,11 +153,13 @@ void LPC1768_PWM_update_map_MR(void) {
map_MR[0] = { 0, (uint8_t) (LPC_PWM1->PCR & _BV(8 + P1_18_PWM_channel) ? 1 : 0), P1_18, &LPC_PWM1->MR1, 0, 0, 0 };
map_MR[1] = { 0, (uint8_t) (LPC_PWM1->PCR & _BV(8 + P1_20_PWM_channel) ? 1 : 0), P1_20, &LPC_PWM1->MR2, 0, 0, 0 };
map_MR[2] = { 0, (uint8_t) (LPC_PWM1->PCR & _BV(8 + P1_21_PWM_channel) ? 1 : 0), P1_21, &LPC_PWM1->MR3, 0, 0, 0 };
#if MOTHERBOARD == BOARD_MKS_SBASE
map_MR[3] = { 0, (uint8_t) (LPC_PWM1->PCR & _BV(8 + P1_23_PWM_channel) ? 1 : 0), P1_23, &LPC_PWM1->MR4, 0, 0, 0 };
map_MR[3] = {
#if MB(MKS_SBASE)
0, (uint8_t) (LPC_PWM1->PCR & _BV(8 + P1_23_PWM_channel) ? 1 : 0), P1_23, &LPC_PWM1->MR4, 0, 0, 0
#else
map_MR[3] = { 0, 0, P_NC, &LPC_PWM1->MR4, 0, 0, 0 };
0, 0, P_NC, &LPC_PWM1->MR4, 0, 0, 0
#endif
};
map_MR[4] = { 0, (uint8_t) (LPC_PWM1->PCR & _BV(8 + P2_04_PWM_channel) ? 1 : 0), P2_04, &LPC_PWM1->MR5, 0, 0, 0 };
map_MR[5] = { 0, (uint8_t) (LPC_PWM1->PCR & _BV(8 + P2_05_PWM_channel) ? 1 : 0), P2_05, &LPC_PWM1->MR6, 0, 0, 0 };
}
@ -212,7 +214,7 @@ void LPC1768_PWM_init(void) {
LPC_PWM1->MR0 = LPC_PWM1_MR0; // TC resets every 19,999 + 1 cycles - sets PWM cycle(Ton+Toff) to 20 mS
// MR0 must be set before TCR enables the PWM
LPC_PWM1->TCR = _BV(SBIT_CNTEN) | _BV(SBIT_CNTRST) | _BV(SBIT_PWMEN); // Enable counters, reset counters, set mode to PWM
LPC_PWM1->TCR &= ~(_BV(SBIT_CNTRST)); // Take counters out of reset
CBI(LPC_PWM1->TCR, SBIT_CNTRST); // Take counters out of reset
LPC_PWM1->PR = LPC_PWM1_PR;
LPC_PWM1->MCR = _BV(SBIT_PWMMR0R) | _BV(0); // Reset TC if it matches MR0, disable all interrupts except for MR0
LPC_PWM1->CTCR = 0; // Disable counter mode (enable PWM mode)
@ -280,42 +282,42 @@ bool LPC1768_PWM_detach_pin(pin_t pin) {
// OK to make these changes before the MR0 interrupt
switch(pin) {
case P1_23: // MKS Sbase Servo 0, PWM1 channel 4 (J3-8 PWM1.4)
LPC_PWM1->PCR &= ~(_BV(8 + P1_23_PWM_channel)); // disable PWM1 module control of this pin
CBI(LPC_PWM1->PCR, 8 + P1_23_PWM_channel); // disable PWM1 module control of this pin
map_MR[P1_23_PWM_channel - 1].PCR_bit = 0;
LPC_PINCON->PINSEL3 &= ~(0x3 << 14); // return pin to general purpose I/O
map_MR[P1_23_PWM_channel - 1].PINSEL_bits = 0;
map_MR[P1_23_PWM_channel - 1].map_PWM_INT = 0; // 0 - available for interrupts, 1 - in use by PWM
break;
case P1_20: // Servo 0, PWM1 channel 2 (Pin 11 P1.20 PWM1.2)
LPC_PWM1->PCR &= ~(_BV(8 + P1_20_PWM_channel)); // disable PWM1 module control of this pin
CBI(LPC_PWM1->PCR, 8 + P1_20_PWM_channel); // disable PWM1 module control of this pin
map_MR[P1_20_PWM_channel - 1].PCR_bit = 0;
LPC_PINCON->PINSEL3 &= ~(0x3 << 8); // return pin to general purpose I/O
map_MR[P1_20_PWM_channel - 1].PINSEL_bits = 0;
map_MR[P1_20_PWM_channel - 1].map_PWM_INT = 0; // 0 - available for interrupts, 1 - in use by PWM
break;
case P1_21: // Servo 1, PWM1 channel 3 (Pin 6 P1.21 PWM1.3)
LPC_PWM1->PCR &= ~(_BV(8 + P1_21_PWM_channel)); // disable PWM1 module control of this pin
CBI(LPC_PWM1->PCR, 8 + P1_21_PWM_channel); // disable PWM1 module control of this pin
map_MR[P1_21_PWM_channel - 1].PCR_bit = 0;
LPC_PINCON->PINSEL3 &= ~(0x3 << 10); // return pin to general purpose I/O
map_MR[P1_21_PWM_channel - 1].PINSEL_bits = 0;
map_MR[P1_21_PWM_channel - 1].map_PWM_INT = 0; // 0 - available for interrupts, 1 - in use by PWM
break;
case P1_18: // Servo 3, PWM1 channel 1 (Pin 4 P1.18 PWM1.1)
LPC_PWM1->PCR &= ~(_BV(8 + P1_18_PWM_channel)); // disable PWM1 module control of this pin
CBI(LPC_PWM1->PCR, 8 + P1_18_PWM_channel); // disable PWM1 module control of this pin
map_MR[P1_18_PWM_channel - 1].PCR_bit = 0;
LPC_PINCON->PINSEL3 &= ~(0x3 << 4); // return pin to general purpose I/O
map_MR[P1_18_PWM_channel - 1].PINSEL_bits = 0;
map_MR[P1_18_PWM_channel - 1].map_PWM_INT = 0; // 0 - available for interrupts, 1 - in use by PWM
break;
case P2_04: // D9 FET, PWM1 channel 5 (Pin 9 P2_04 PWM1.5)
LPC_PWM1->PCR &= ~(_BV(8 + P2_04_PWM_channel)); // disable PWM1 module control of this pin
CBI(LPC_PWM1->PCR, 8 + P2_04_PWM_channel); // disable PWM1 module control of this pin
map_MR[P2_04_PWM_channel - 1].PCR_bit = 0;
LPC_PINCON->PINSEL4 &= ~(0x3 << 10); // return pin to general purpose I/O
map_MR[P2_04_PWM_channel - 1].PINSEL_bits = 0;
map_MR[P2_04_PWM_channel - 1].map_PWM_INT = 0; // 0 - available for interrupts, 1 - in use by PWM
break;
case P2_05: // D10 FET, PWM1 channel 6 (Pin 10 P2_05 PWM1.6)
LPC_PWM1->PCR &= ~(_BV(8 + P2_05_PWM_channel)); // disable PWM1 module control of this pin
CBI(LPC_PWM1->PCR, 8 + P2_05_PWM_channel); // disable PWM1 module control of this pin
map_MR[P2_05_PWM_channel - 1].PCR_bit = 0;
LPC_PINCON->PINSEL4 &= ~(0x3 << 4); // return pin to general purpose I/O
map_MR[P2_05_PWM_channel - 1].PINSEL_bits = 0;

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