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@ -101,8 +101,24 @@ bool SDIO_ReadBlock_DMA(uint32_t blockAddress, uint8_t *data) { |
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return false; |
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} |
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while (!SDIO_GET_FLAG(SDIO_STA_DATAEND | SDIO_STA_TRX_ERROR_FLAGS)) {} |
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while (!SDIO_GET_FLAG(SDIO_STA_DATAEND | SDIO_STA_TRX_ERROR_FLAGS)) { /* wait */ } |
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//If there were SDIO errors, do not wait DMA.
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if (SDIO->STA & SDIO_STA_TRX_ERROR_FLAGS) { |
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SDIO_CLEAR_FLAG(SDIO_ICR_CMD_FLAGS | SDIO_ICR_DATA_FLAGS); |
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dma_disable(SDIO_DMA_DEV, SDIO_DMA_CHANNEL); |
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return false; |
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} |
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//Wait for DMA transaction to complete
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while ((DMA2_BASE->ISR & (DMA_ISR_TEIF4|DMA_ISR_TCIF4)) == 0 ) { /* wait */ } |
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if (DMA2_BASE->ISR & DMA_ISR_TEIF4) { |
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dma_disable(SDIO_DMA_DEV, SDIO_DMA_CHANNEL); |
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SDIO_CLEAR_FLAG(SDIO_ICR_CMD_FLAGS | SDIO_ICR_DATA_FLAGS); |
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return false; |
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} |
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dma_disable(SDIO_DMA_DEV, SDIO_DMA_CHANNEL); |
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if (SDIO->STA & SDIO_STA_RXDAVL) { |
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@ -146,7 +162,7 @@ bool SDIO_WriteBlock(uint32_t blockAddress, const uint8_t *data) { |
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sdio_setup_transfer(SDIO_DATA_TIMEOUT * (F_CPU / 1000U), 512U, SDIO_BLOCKSIZE_512 | SDIO_DCTRL_DMAEN | SDIO_DCTRL_DTEN); |
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while (!SDIO_GET_FLAG(SDIO_STA_DATAEND | SDIO_STA_TRX_ERROR_FLAGS)) {} |
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while (!SDIO_GET_FLAG(SDIO_STA_DATAEND | SDIO_STA_TRX_ERROR_FLAGS)) { /* wait */ } |
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dma_disable(SDIO_DMA_DEV, SDIO_DMA_CHANNEL); |
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