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@ -29,28 +29,43 @@ |
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// Copied from ~/.platformio/packages/framework-arduinoststm32-maple/STM32F1/system/libmaple/usart_private.h
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// Copied from ~/.platformio/packages/framework-arduinoststm32-maple/STM32F1/system/libmaple/usart_private.h
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// Changed to handle Emergency Parser
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// Changed to handle Emergency Parser
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static inline __always_inline void my_usart_irq(ring_buffer *rb, ring_buffer *wb, usart_reg_map *regs, MarlinSerial &serial) { |
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static inline __always_inline void my_usart_irq(ring_buffer *rb, ring_buffer *wb, usart_reg_map *regs, MarlinSerial &serial) { |
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/* Handle RXNEIE and TXEIE interrupts.
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/* Handle RXNEIE and TXEIE interrupts.
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* RXNE signifies availability of a byte in DR. |
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* RXNE signifies availability of a byte in DR. |
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* |
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* |
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* See table 198 (sec 27.4, p809) in STM document RM0008 rev 15. |
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* See table 198 (sec 27.4, p809) in STM document RM0008 rev 15. |
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* We enable RXNEIE. |
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* We enable RXNEIE. |
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*/ |
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*/ |
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if ((regs->CR1 & USART_CR1_RXNEIE) && (regs->SR & USART_SR_RXNE)) { |
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uint32_t srflags = regs->SR, cr1its = regs->CR1; |
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uint8_t c = (uint8)regs->DR; |
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#ifdef USART_SAFE_INSERT |
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if ((cr1its & USART_CR1_RXNEIE) && (srflags & USART_SR_RXNE)) { |
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// If the buffer is full and the user defines USART_SAFE_INSERT,
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if (srflags & USART_SR_FE || srflags & USART_SR_PE ) { |
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// ignore new bytes.
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// framing error or parity error
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rb_safe_insert(rb, c); |
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regs->DR; // Read and throw away the data, which also clears FE and PE
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#else |
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} |
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// By default, push bytes around in the ring buffer.
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else { |
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rb_push_insert(rb, c); |
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uint8_t c = (uint8)regs->DR; |
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#endif |
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#ifdef USART_SAFE_INSERT |
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#if ENABLED(EMERGENCY_PARSER) |
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// If the buffer is full and the user defines USART_SAFE_INSERT,
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emergency_parser.update(serial.emergency_state, c); |
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// ignore new bytes.
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#endif |
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rb_safe_insert(rb, c); |
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#else |
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// By default, push bytes around in the ring buffer.
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rb_push_insert(rb, c); |
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#endif |
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#if ENABLED(EMERGENCY_PARSER) |
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emergency_parser.update(serial.emergency_state, c); |
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#endif |
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} |
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} |
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else if (srflags & USART_SR_ORE) { |
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// overrun and empty data, just do a dummy read to clear ORE
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// and prevent a raise condition where a continous interrupt stream (due to ORE set) occurs
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// (see chapter "Overrun error" ) in STM32 reference manual
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regs->DR; |
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} |
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} |
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// TXE signifies readiness to send a byte to DR.
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// TXE signifies readiness to send a byte to DR.
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if ((regs->CR1 & USART_CR1_TXEIE) && (regs->SR & USART_SR_TXE)) { |
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if ((cr1its & USART_CR1_TXEIE) && (srflags & USART_SR_TXE)) { |
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if (!rb_is_empty(wb)) |
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if (!rb_is_empty(wb)) |
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regs->DR=rb_remove(wb); |
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regs->DR=rb_remove(wb); |
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else |
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else |
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