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@ -24,28 +24,30 @@ |
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#if ENABLED(USE_WATCHDOG) |
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#if ENABLED(USE_WATCHDOG) |
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#include "watchdog.h" |
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#include "watchdog.h" |
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void watchdog_init() { |
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#define WDT_TIMEOUT_REG TERN(WATCHDOG_DURATION_8S, WDT_CONFIG_PER_CYC8192, WDT_CONFIG_PER_CYC4096) // 4 or 8 second timeout
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// The low-power oscillator used by the WDT runs at 32,768 Hz with
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// a 1:32 prescale, thus 1024 Hz, though probably not super precise.
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// Setup WDT clocks
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void watchdog_init() { |
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MCLK->APBAMASK.bit.OSC32KCTRL_ = true; |
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// The low-power oscillator used by the WDT runs at 32,768 Hz with
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MCLK->APBAMASK.bit.WDT_ = true; |
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// a 1:32 prescale, thus 1024 Hz, though probably not super precise.
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OSC32KCTRL->OSCULP32K.bit.EN1K = true; // Enable out 1K (this is what WDT uses)
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WDT->CTRLA.bit.ENABLE = false; // Disable watchdog for config
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// Setup WDT clocks
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SYNC(WDT->SYNCBUSY.bit.ENABLE); |
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MCLK->APBAMASK.bit.OSC32KCTRL_ = true; |
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MCLK->APBAMASK.bit.WDT_ = true; |
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OSC32KCTRL->OSCULP32K.bit.EN1K = true; // Enable out 1K (this is what WDT uses)
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WDT->INTENCLR.reg = WDT_INTENCLR_EW; // Disable early warning interrupt
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WDT->CTRLA.bit.ENABLE = false; // Disable watchdog for config
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WDT->CONFIG.reg = WDT_CONFIG_PER_CYC4096; // Set at least 4s period for chip reset
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SYNC(WDT->SYNCBUSY.bit.ENABLE); |
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HAL_watchdog_refresh(); |
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WDT->INTENCLR.reg = WDT_INTENCLR_EW; // Disable early warning interrupt
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WDT->CONFIG.reg = WDT_TIMEOUT_REG; // Set a 4s or 8s period for chip reset
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WDT->CTRLA.reg = WDT_CTRLA_ENABLE; // Start watchdog now in normal mode
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HAL_watchdog_refresh(); |
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SYNC(WDT->SYNCBUSY.bit.ENABLE); |
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} |
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WDT->CTRLA.reg = WDT_CTRLA_ENABLE; // Start watchdog now in normal mode
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SYNC(WDT->SYNCBUSY.bit.ENABLE); |
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} |
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#endif // USE_WATCHDOG
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#endif // USE_WATCHDOG
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