From 5cbdf51b4a8551893a3692c413aacef65541e71d Mon Sep 17 00:00:00 2001
From: Scott Lahteine <github@thinkyhead.com>
Date: Mon, 3 May 2021 20:09:21 -0500
Subject: [PATCH] Apply SBI/CBI/TEST in HAL

---
 Marlin/src/HAL/LPC1768/main.cpp          |  2 +-
 Marlin/src/HAL/STM32/HAL_MinSerial.cpp   |  4 ++--
 Marlin/src/HAL/STM32/tft/tft_ltdc.cpp    | 25 +++++++++++-------------
 Marlin/src/HAL/STM32F1/HAL_MinSerial.cpp |  2 +-
 4 files changed, 15 insertions(+), 18 deletions(-)

diff --git a/Marlin/src/HAL/LPC1768/main.cpp b/Marlin/src/HAL/LPC1768/main.cpp
index 08fb1a1ed5..ef0dc42c78 100644
--- a/Marlin/src/HAL/LPC1768/main.cpp
+++ b/Marlin/src/HAL/LPC1768/main.cpp
@@ -117,7 +117,7 @@ void HAL_init() {
     PinCfg.Pinmode = 2;    // no pull-up/pull-down
     PINSEL_ConfigPin(&PinCfg);
     // now set CLKOUT_EN bit
-    LPC_SC->CLKOUTCFG |= (1<<8);
+    SBI(LPC_SC->CLKOUTCFG, 8);
   #endif
 
   USB_Init();                               // USB Initialization
diff --git a/Marlin/src/HAL/STM32/HAL_MinSerial.cpp b/Marlin/src/HAL/STM32/HAL_MinSerial.cpp
index 823bb6e8f5..7268eed591 100644
--- a/Marlin/src/HAL/STM32/HAL_MinSerial.cpp
+++ b/Marlin/src/HAL/STM32/HAL_MinSerial.cpp
@@ -71,8 +71,8 @@ static void TXBegin() {
       volatile uint32_t ICER[32];
     };
 
-    NVICMin * nvicBase = (NVICMin*)0xE000E100;
-    nvicBase->ICER[nvicIndex / 32] |= _BV32(nvicIndex % 32);
+    NVICMin *nvicBase = (NVICMin*)0xE000E100;
+    SBI32(nvicBase->ICER[nvicIndex >> 5], nvicIndex & 0x1F);
 
     // We NEED memory barriers to ensure Interrupts are actually disabled!
     // ( https://dzone.com/articles/nvic-disabling-interrupts-on-arm-cortex-m-and-the )
diff --git a/Marlin/src/HAL/STM32/tft/tft_ltdc.cpp b/Marlin/src/HAL/STM32/tft/tft_ltdc.cpp
index 6039593f46..c1a56101ad 100644
--- a/Marlin/src/HAL/STM32/tft/tft_ltdc.cpp
+++ b/Marlin/src/HAL/STM32/tft/tft_ltdc.cpp
@@ -45,7 +45,6 @@
 #define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
 #define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE     ((uint16_t)0x0200)
 
-
 void SDRAM_Initialization_Sequence(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command) {
 
   __IO uint32_t tmpmrd =0;
@@ -192,7 +191,7 @@ void LTDC_Config() {
 
   hltdc_F.Instance = LTDC;
 
-/* Layer0 Configuration ------------------------------------------------------*/
+  /* Layer0 Configuration ------------------------------------------------------*/
 
   /* Windowing configuration */
   pLayerCfg.WindowX0 = 0;
@@ -289,22 +288,21 @@ void TFT_LTDC::DrawRect(uint16_t sx, uint16_t sy, uint16_t ex, uint16_t ey, uint
   uint16_t offline = TFT_WIDTH - (ex - sx);
   uint32_t addr = (uint32_t)&framebuffer[(TFT_WIDTH * sy) + sx];
 
-  DMA2D->CR &= ~(1 << 0);
+  CBI(DMA2D->CR, 0);
   DMA2D->CR = 3 << 16;
   DMA2D->OPFCCR = 0X02;
   DMA2D->OOR = offline;
   DMA2D->OMAR = addr;
   DMA2D->NLR = (ey - sy) | ((ex - sx) << 16);
   DMA2D->OCOLR = color;
-  DMA2D->CR |= 1<<0;
+  SBI(DMA2D->CR, 0);
 
   uint32_t timeout = 0;
-  while((DMA2D->ISR & (1<<1)) == 0)
-  {
+  while (!TEST(DMA2D->ISR, 1)) {
     timeout++;
-    if(timeout>0X1FFFFF)break;
+    if (timeout > 0x1FFFFF) break;
   }
-  DMA2D->IFCR |= 1<<1;
+  SBI(DMA2D->IFCR, 1);
 }
 
 void TFT_LTDC::DrawImage(uint16_t sx, uint16_t sy, uint16_t ex, uint16_t ey, uint16_t *colors) {
@@ -314,7 +312,7 @@ void TFT_LTDC::DrawImage(uint16_t sx, uint16_t sy, uint16_t ex, uint16_t ey, uin
   uint16_t offline = TFT_WIDTH - (ex - sx);
   uint32_t addr = (uint32_t)&framebuffer[(TFT_WIDTH * sy) + sx];
 
-  DMA2D->CR &= ~(1 << 0);
+  CBI(DMA2D->CR, 0)
   DMA2D->CR = 0 << 16;
   DMA2D->FGPFCCR = 0X02;
   DMA2D->FGOR = 0;
@@ -322,15 +320,14 @@ void TFT_LTDC::DrawImage(uint16_t sx, uint16_t sy, uint16_t ex, uint16_t ey, uin
   DMA2D->FGMAR = (uint32_t)colors;
   DMA2D->OMAR = addr;
   DMA2D->NLR = (ey - sy) | ((ex - sx) << 16);
-  DMA2D->CR |= 1<<0;
+  SBI(DMA2D->CR, 0);
 
   uint32_t timeout = 0;
-  while((DMA2D->ISR & (1<<1)) == 0)
-  {
+  while (!TEST(DMA2D->ISR, 1)) {
     timeout++;
-    if(timeout>0X1FFFFF)break;
+    if (timeout > 0x1FFFFF) break;
   }
-  DMA2D->IFCR |= 1<<1;
+  SBI(DMA2D->IFCR, 1);
 }
 
 void TFT_LTDC::WriteData(uint16_t data) {
diff --git a/Marlin/src/HAL/STM32F1/HAL_MinSerial.cpp b/Marlin/src/HAL/STM32F1/HAL_MinSerial.cpp
index 2cb75bb1e9..0fc3d014d4 100644
--- a/Marlin/src/HAL/STM32F1/HAL_MinSerial.cpp
+++ b/Marlin/src/HAL/STM32F1/HAL_MinSerial.cpp
@@ -55,7 +55,7 @@ static void TXBegin() {
     nvic_irq_disable(dev->irq_num);
 
     // Use this if removing libmaple
-    //NVIC_BASE->ICER[1] |= _BV(irq - 32);
+    //SBI(NVIC_BASE->ICER[1], irq - 32);
 
     // We NEED memory barriers to ensure Interrupts are actually disabled!
     // ( https://dzone.com/articles/nvic-disabling-interrupts-on-arm-cortex-m-and-the )