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@ -142,7 +142,7 @@ UnwResult UnwStartArm(UnwState * const state) { |
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/* MRS */ |
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else if ((instr & 0xFFBF0FFF) == 0xE10F0000) { |
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#if defined(UNW_DEBUG) |
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#ifdef UNW_DEBUG |
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bool R = (instr & 0x00400000) ? true : false; |
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#endif |
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uint8_t rd = (instr & 0x0000F000) >> 12; |
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@ -154,7 +154,7 @@ UnwResult UnwStartArm(UnwState * const state) { |
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} |
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/* MSR */ |
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else if ((instr & 0xFFB0F000) == 0xE120F000) { |
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#if defined(UNW_DEBUG) |
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#ifdef UNW_DEBUG |
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bool R = (instr & 0x00400000) ? true : false; |
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UnwPrintd2("MSR %s_?, ???", R ? "SPSR" : "CPSR"); |
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@ -172,7 +172,7 @@ UnwResult UnwStartArm(UnwState * const state) { |
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else if (isDataProc(instr)) { |
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bool I = (instr & 0x02000000) ? true : false; |
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uint8_t opcode = (instr & 0x01E00000) >> 21; |
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#if defined(UNW_DEBUG) |
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#ifdef UNW_DEBUG |
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bool S = (instr & 0x00100000) ? true : false; |
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#endif |
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uint8_t rn = (instr & 0x000F0000) >> 16; |
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@ -220,7 +220,7 @@ UnwResult UnwStartArm(UnwState * const state) { |
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uint8_t regShift = (operand2 & 0x0010) ? true : false; |
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uint8_t shiftType = (operand2 & 0x0060) >> 5; |
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uint32_t shiftDist; |
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#if defined(UNW_DEBUG) |
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#ifdef UNW_DEBUG |
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const char * const shiftMnu[4] = { "LSL", "LSR", "ASR", "ROR" }; |
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#endif |
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UnwPrintd2("r%d ", rm); |
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@ -453,7 +453,7 @@ UnwResult UnwStartArm(UnwState * const state) { |
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bool addrValid = M_IsOriginValid(state->regData[baseReg].o); |
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int8_t r; |
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#if defined(UNW_DEBUG) |
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#ifdef UNW_DEBUG |
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/* Display the instruction */ |
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if (L) { |
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UnwPrintd6("LDM%c%c r%d%s, {reglist}%s\n", P ? 'E' : 'F', U ? 'D' : 'A', baseReg, W ? "!" : "", S ? "^" : ""); |
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