From 4454d80276f4097f2e9713848df3efd9e5b431f0 Mon Sep 17 00:00:00 2001 From: AnHardt Date: Tue, 7 Jun 2016 13:45:35 +0200 Subject: [PATCH] Decrease the needed nops to 1 by shitfing the left shift into the high phase. ``` 2 cbi 0x2,1 ;set CLK // 1 in r18,__SREG__ //1 1-3 sbrc r24,7 //2-4 2 rjmp .L19 //4 1 cli .L19: //5 2 lds r25,258 lds r25,258 //7 1 andi r25,lo8(-2) ori r25,lo8(1) //8 2 sts 258,r25 sts 258,r25 //10 1 out __SREG__,r18 out __SREG__,r18 //11 2 .L3: rjmp .L3 //13 //2 2 sbi 0x2,1 ;reset CLK // //13-15 //2-4 1 lsl r24 ; val //1 1 nop //2 2 cbi 0x2,1 ;set CLK //4 ... ``` --- Marlin/ultralcd_st7920_u8glib_rrd.h | 26 ++++++++++++-------------- 1 file changed, 12 insertions(+), 14 deletions(-) diff --git a/Marlin/ultralcd_st7920_u8glib_rrd.h b/Marlin/ultralcd_st7920_u8glib_rrd.h index 1df6343ed9..9611efe6c5 100644 --- a/Marlin/ultralcd_st7920_u8glib_rrd.h +++ b/Marlin/ultralcd_st7920_u8glib_rrd.h @@ -41,7 +41,6 @@ #include //set optimization so ARDUINO optimizes this file -#pragma GCC push_options #pragma GCC optimize (3) #define DELAY_0_NOP ; @@ -64,9 +63,9 @@ #define ST7920_DELAY_2 DELAY_0_NOP #endif #ifndef ST7920_DELAY_3 - #define ST7920_DELAY_3 DELAY_2_NOP + #define ST7920_DELAY_3 DELAY_1_NOP #endif -#elif MOTHERBOARD == BOARD_3DRAG +#elif (MOTHERBOARD == BOARD_3DRAG) || (MOTHERBOARD == BOARD_K8200) #ifndef ST7920_DELAY_1 #define ST7920_DELAY_1 DELAY_0_NOP #endif @@ -74,7 +73,7 @@ #define ST7920_DELAY_2 DELAY_0_NOP #endif #ifndef ST7920_DELAY_3 - #define ST7920_DELAY_3 DELAY_2_NOP + #define ST7920_DELAY_3 DELAY_1_NOP #endif #elif F_CPU == 16000000 #ifndef ST7920_DELAY_1 @@ -84,7 +83,7 @@ #define ST7920_DELAY_2 DELAY_0_NOP #endif #ifndef ST7920_DELAY_3 - #define ST7920_DELAY_3 DELAY_2_NOP + #define ST7920_DELAY_3 DELAY_1_NOP #endif #else #error "No valid condition for delays in 'ultralcd_st7920_u8glib_rrd.h'" @@ -94,63 +93,62 @@ static void ST7920_SWSPI_SND_8BIT(uint8_t val) { WRITE(ST7920_CLK_PIN,0); ST7920_DELAY_1 WRITE(ST7920_DAT_PIN,val&0x80); - val<<=1; ST7920_DELAY_2 WRITE(ST7920_CLK_PIN,1); + val<<=1; ST7920_DELAY_3 WRITE(ST7920_CLK_PIN,0); ST7920_DELAY_1 WRITE(ST7920_DAT_PIN,val&0x80); - val<<=1; ST7920_DELAY_2 WRITE(ST7920_CLK_PIN,1); + val<<=1; ST7920_DELAY_3 WRITE(ST7920_CLK_PIN,0); ST7920_DELAY_1 WRITE(ST7920_DAT_PIN,val&0x80); - val<<=1; ST7920_DELAY_2 WRITE(ST7920_CLK_PIN,1); + val<<=1; ST7920_DELAY_3 WRITE(ST7920_CLK_PIN,0); ST7920_DELAY_1 WRITE(ST7920_DAT_PIN,val&0x80); - val<<=1; ST7920_DELAY_2 WRITE(ST7920_CLK_PIN,1); + val<<=1; ST7920_DELAY_3 WRITE(ST7920_CLK_PIN,0); ST7920_DELAY_1 WRITE(ST7920_DAT_PIN,val&0x80); - val<<=1; ST7920_DELAY_2 WRITE(ST7920_CLK_PIN,1); + val<<=1; ST7920_DELAY_3 WRITE(ST7920_CLK_PIN,0); ST7920_DELAY_1 WRITE(ST7920_DAT_PIN,val&0x80); - val<<=1; ST7920_DELAY_2 WRITE(ST7920_CLK_PIN,1); + val<<=1; ST7920_DELAY_3 WRITE(ST7920_CLK_PIN,0); ST7920_DELAY_1 WRITE(ST7920_DAT_PIN,val&0x80); - val<<=1; ST7920_DELAY_2 WRITE(ST7920_CLK_PIN,1); + val<<=1; ST7920_DELAY_3 WRITE(ST7920_CLK_PIN,0); ST7920_DELAY_1 WRITE(ST7920_DAT_PIN,val&0x80); - val<<=1; ST7920_DELAY_2 WRITE(ST7920_CLK_PIN,1); } @@ -234,7 +232,7 @@ class U8GLIB_ST7920_128X64_RRD : public U8GLIB { U8GLIB_ST7920_128X64_RRD(uint8_t dummy) : U8GLIB(&u8g_dev_st7920_128x64_rrd_sw_spi) { UNUSED(dummy); } }; -#pragma GCC pop_options +#pragma GCC reset_options #endif //U8GLIB_ST7920 #endif //ULCDST7920_H