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@ -346,7 +346,6 @@ extern "C" { |
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void UART0_IRQHandler (void) |
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{ |
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uint8_t IIRValue, LSRValue; |
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uint8_t Dummy = Dummy; |
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IIRValue = LPC_UART0->IIR; |
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@ -354,59 +353,59 @@ void UART0_IRQHandler (void) |
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IIRValue &= 0x07; /* check bit 1~3, interrupt identification */ |
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if ( IIRValue == IIR_RLS ) /* Receive Line Status */ |
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{ |
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LSRValue = LPC_UART0->LSR; |
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/* Receive Line Status */ |
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if ( LSRValue & (LSR_OE|LSR_PE|LSR_FE|LSR_RXFE|LSR_BI) ) |
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{ |
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/* There are errors or break interrupt */ |
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/* Read LSR will clear the interrupt */ |
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UART0Status = LSRValue; |
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Dummy = LPC_UART0->RBR; /* Dummy read on RX to clear
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interrupt, then bail out */ |
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return; |
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} |
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if ( LSRValue & LSR_RDR ) /* Receive Data Ready */ |
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{ |
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/* If no error on RLS, normal ready, save into the data buffer. */ |
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/* Note: read RBR will clear the interrupt */ |
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if ((UART0RxQueueWritePos+1) % UARTRXQUEUESIZE != UART0RxQueueReadPos) |
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{ |
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UART0Buffer[UART0RxQueueWritePos] = LPC_UART0->RBR; |
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UART0RxQueueWritePos = (UART0RxQueueWritePos+1) % UARTRXQUEUESIZE; |
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} |
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else |
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dummy = LPC_UART0->RBR;; |
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} |
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LSRValue = LPC_UART0->LSR; |
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/* Receive Line Status */ |
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if ( LSRValue & (LSR_OE|LSR_PE|LSR_FE|LSR_RXFE|LSR_BI) ) |
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{ |
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/* There are errors or break interrupt */ |
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/* Read LSR will clear the interrupt */ |
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UART0Status = LSRValue; |
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dummy = LPC_UART0->RBR; /* Dummy read on RX to clear
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interrupt, then bail out */ |
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return; |
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} |
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if ( LSRValue & LSR_RDR ) /* Receive Data Ready */ |
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{ |
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/* If no error on RLS, normal ready, save into the data buffer. */ |
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/* Note: read RBR will clear the interrupt */ |
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if ((UART0RxQueueWritePos+1) % UARTRXQUEUESIZE != UART0RxQueueReadPos) |
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{ |
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UART0Buffer[UART0RxQueueWritePos] = LPC_UART0->RBR; |
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UART0RxQueueWritePos = (UART0RxQueueWritePos+1) % UARTRXQUEUESIZE; |
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} |
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else |
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dummy = LPC_UART0->RBR; |
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} |
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} |
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else if ( IIRValue == IIR_RDA ) /* Receive Data Available */ |
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{ |
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/* Receive Data Available */ |
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/* Receive Data Available */ |
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if ((UART0RxQueueWritePos+1) % UARTRXQUEUESIZE != UART0RxQueueReadPos) |
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{ |
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UART0Buffer[UART0RxQueueWritePos] = LPC_UART0->RBR; |
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UART0RxQueueWritePos = (UART0RxQueueWritePos+1) % UARTRXQUEUESIZE; |
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} |
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else |
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dummy = LPC_UART1->RBR;; |
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dummy = LPC_UART1->RBR; |
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} |
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else if ( IIRValue == IIR_CTI ) /* Character timeout indicator */ |
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{ |
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/* Character Time-out indicator */ |
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UART0Status |= 0x100; /* Bit 9 as the CTI error */ |
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/* Character Time-out indicator */ |
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UART0Status |= 0x100; /* Bit 9 as the CTI error */ |
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} |
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else if ( IIRValue == IIR_THRE ) /* THRE, transmit holding register empty */ |
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{ |
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/* THRE interrupt */ |
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LSRValue = LPC_UART0->LSR; /* Check status in the LSR to see if
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valid data in U0THR or not */ |
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if ( LSRValue & LSR_THRE ) |
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{ |
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UART0TxEmpty = 1; |
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} |
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else |
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{ |
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UART0TxEmpty = 0; |
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} |
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/* THRE interrupt */ |
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LSRValue = LPC_UART0->LSR; /* Check status in the LSR to see if
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valid data in U0THR or not */ |
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if ( LSRValue & LSR_THRE ) |
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{ |
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UART0TxEmpty = 1; |
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} |
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else |
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{ |
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UART0TxEmpty = 0; |
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} |
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} |
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} |
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@ -422,7 +421,6 @@ void UART0_IRQHandler (void) |
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void UART1_IRQHandler (void) |
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{ |
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uint8_t IIRValue, LSRValue; |
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uint8_t Dummy = Dummy; |
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IIRValue = LPC_UART1->IIR; |
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@ -430,61 +428,60 @@ void UART1_IRQHandler (void) |
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IIRValue &= 0x07; /* check bit 1~3, interrupt identification */ |
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if ( IIRValue == IIR_RLS ) /* Receive Line Status */ |
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{ |
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LSRValue = LPC_UART1->LSR; |
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/* Receive Line Status */ |
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if ( LSRValue & (LSR_OE|LSR_PE|LSR_FE|LSR_RXFE|LSR_BI) ) |
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{ |
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/* There are errors or break interrupt */ |
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/* Read LSR will clear the interrupt */ |
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UART1Status = LSRValue; |
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Dummy = LPC_UART1->RBR; /* Dummy read on RX to clear
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interrupt, then bail out */ |
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return; |
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} |
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if ( LSRValue & LSR_RDR ) /* Receive Data Ready */ |
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{ |
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/* If no error on RLS, normal ready, save into the data buffer. */ |
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/* Note: read RBR will clear the interrupt */ |
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if ((UART1RxQueueWritePos+1) % UARTRXQUEUESIZE != UART1RxQueueReadPos) |
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{ |
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UART1Buffer[UART1RxQueueWritePos] = LPC_UART1->RBR; |
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UART1RxQueueWritePos =(UART1RxQueueWritePos+1) % UARTRXQUEUESIZE; |
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} |
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else |
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dummy = LPC_UART1->RBR;; |
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} |
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LSRValue = LPC_UART1->LSR; |
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/* Receive Line Status */ |
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if ( LSRValue & (LSR_OE|LSR_PE|LSR_FE|LSR_RXFE|LSR_BI) ) |
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{ |
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/* There are errors or break interrupt */ |
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/* Read LSR will clear the interrupt */ |
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UART1Status = LSRValue; |
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dummy = LPC_UART1->RBR; /* Dummy read on RX to clear
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interrupt, then bail out */ |
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return; |
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} |
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if ( LSRValue & LSR_RDR ) /* Receive Data Ready */ |
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{ |
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/* If no error on RLS, normal ready, save into the data buffer. */ |
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/* Note: read RBR will clear the interrupt */ |
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if ((UART1RxQueueWritePos+1) % UARTRXQUEUESIZE != UART1RxQueueReadPos) |
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{ |
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UART1Buffer[UART1RxQueueWritePos] = LPC_UART1->RBR; |
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UART1RxQueueWritePos =(UART1RxQueueWritePos+1) % UARTRXQUEUESIZE; |
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} |
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else |
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dummy = LPC_UART1->RBR; |
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} |
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} |
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else if ( IIRValue == IIR_RDA ) /* Receive Data Available */ |
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{ |
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/* Receive Data Available */ |
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/* Receive Data Available */ |
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if ((UART1RxQueueWritePos+1) % UARTRXQUEUESIZE != UART1RxQueueReadPos) |
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{ |
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UART1Buffer[UART1RxQueueWritePos] = LPC_UART1->RBR; |
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UART1RxQueueWritePos = (UART1RxQueueWritePos+1) % UARTRXQUEUESIZE; |
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} |
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else |
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dummy = LPC_UART1->RBR;; |
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dummy = LPC_UART1->RBR; |
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} |
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else if ( IIRValue == IIR_CTI ) /* Character timeout indicator */ |
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{ |
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/* Character Time-out indicator */ |
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UART1Status |= 0x100; /* Bit 9 as the CTI error */ |
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} |
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else if ( IIRValue == IIR_THRE ) /* THRE, transmit holding register empty */ |
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{ |
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/* THRE interrupt */ |
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LSRValue = LPC_UART1->LSR; /* Check status in the LSR to see if
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valid data in U0THR or not */ |
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if ( LSRValue & LSR_THRE ) |
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{ |
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UART1TxEmpty = 1; |
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} |
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else |
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{ |
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UART1TxEmpty = 0; |
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} |
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/* Character Time-out indicator */ |
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UART1Status |= 0x100; /* Bit 9 as the CTI error */ |
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} |
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else if ( IIRValue == IIR_THRE ) /* THRE, transmit holding register empty */ |
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{ |
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/* THRE interrupt */ |
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LSRValue = LPC_UART1->LSR; /* Check status in the LSR to see if
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valid data in U0THR or not */ |
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if ( LSRValue & LSR_THRE ) |
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{ |
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UART1TxEmpty = 1; |
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} |
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else |
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{ |
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UART1TxEmpty = 0; |
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} |
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} |
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} |
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/*****************************************************************************
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** Function name: UART2_IRQHandler |
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@ -498,7 +495,6 @@ void UART1_IRQHandler (void) |
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void UART2_IRQHandler (void) |
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{ |
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uint8_t IIRValue, LSRValue; |
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uint8_t Dummy = Dummy; |
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IIRValue = LPC_UART2->IIR; |
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@ -506,57 +502,57 @@ void UART2_IRQHandler (void) |
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IIRValue &= 0x07; /* check bit 1~3, interrupt identification */ |
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if ( IIRValue == IIR_RLS ) /* Receive Line Status */ |
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{ |
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LSRValue = LPC_UART2->LSR; |
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/* Receive Line Status */ |
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if ( LSRValue & (LSR_OE|LSR_PE|LSR_FE|LSR_RXFE|LSR_BI) ) |
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{ |
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/* There are errors or break interrupt */ |
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/* Read LSR will clear the interrupt */ |
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UART2Status = LSRValue; |
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Dummy = LPC_UART2->RBR; /* Dummy read on RX to clear
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interrupt, then bail out */ |
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return; |
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} |
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if ( LSRValue & LSR_RDR ) /* Receive Data Ready */ |
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{ |
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/* If no error on RLS, normal ready, save into the data buffer. */ |
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/* Note: read RBR will clear the interrupt */ |
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if ((UART2RxQueueWritePos+1) % UARTRXQUEUESIZE != UART2RxQueueReadPos) |
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{ |
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UART2Buffer[UART2RxQueueWritePos] = LPC_UART2->RBR; |
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UART2RxQueueWritePos = (UART2RxQueueWritePos+1) % UARTRXQUEUESIZE; |
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} |
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} |
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LSRValue = LPC_UART2->LSR; |
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/* Receive Line Status */ |
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if ( LSRValue & (LSR_OE|LSR_PE|LSR_FE|LSR_RXFE|LSR_BI) ) |
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{ |
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/* There are errors or break interrupt */ |
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/* Read LSR will clear the interrupt */ |
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UART2Status = LSRValue; |
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dummy = LPC_UART2->RBR; /* Dummy read on RX to clear
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interrupt, then bail out */ |
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return; |
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} |
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if ( LSRValue & LSR_RDR ) /* Receive Data Ready */ |
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{ |
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/* If no error on RLS, normal ready, save into the data buffer. */ |
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/* Note: read RBR will clear the interrupt */ |
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if ((UART2RxQueueWritePos+1) % UARTRXQUEUESIZE != UART2RxQueueReadPos) |
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{ |
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UART2Buffer[UART2RxQueueWritePos] = LPC_UART2->RBR; |
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UART2RxQueueWritePos = (UART2RxQueueWritePos+1) % UARTRXQUEUESIZE; |
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} |
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} |
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} |
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else if ( IIRValue == IIR_RDA ) /* Receive Data Available */ |
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{ |
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/* Receive Data Available */ |
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/* Receive Data Available */ |
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if ((UART2RxQueueWritePos+1) % UARTRXQUEUESIZE != UART2RxQueueReadPos) |
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{ |
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UART2Buffer[UART2RxQueueWritePos] = LPC_UART2->RBR; |
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UART2RxQueueWritePos = (UART2RxQueueWritePos+1) % UARTRXQUEUESIZE; |
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} |
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else |
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dummy = LPC_UART2->RBR;; |
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dummy = LPC_UART2->RBR; |
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} |
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else if ( IIRValue == IIR_CTI ) /* Character timeout indicator */ |
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{ |
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/* Character Time-out indicator */ |
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UART2Status |= 0x100; /* Bit 9 as the CTI error */ |
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/* Character Time-out indicator */ |
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UART2Status |= 0x100; /* Bit 9 as the CTI error */ |
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} |
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else if ( IIRValue == IIR_THRE ) /* THRE, transmit holding register empty */ |
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{ |
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/* THRE interrupt */ |
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LSRValue = LPC_UART2->LSR; /* Check status in the LSR to see if
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valid data in U0THR or not */ |
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if ( LSRValue & LSR_THRE ) |
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{ |
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UART2TxEmpty = 1; |
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} |
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else |
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{ |
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UART2TxEmpty = 0; |
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} |
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/* THRE interrupt */ |
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LSRValue = LPC_UART2->LSR; /* Check status in the LSR to see if
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valid data in U0THR or not */ |
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if ( LSRValue & LSR_THRE ) |
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{ |
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UART2TxEmpty = 1; |
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} |
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else |
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{ |
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UART2TxEmpty = 0; |
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} |
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} |
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} |
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/*****************************************************************************
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@ -571,7 +567,6 @@ void UART2_IRQHandler (void) |
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void UART3_IRQHandler (void) |
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{ |
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uint8_t IIRValue, LSRValue; |
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uint8_t Dummy = Dummy; |
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IIRValue = LPC_UART3->IIR; |
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@ -579,57 +574,57 @@ void UART3_IRQHandler (void) |
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IIRValue &= 0x07; /* check bit 1~3, interrupt identification */ |
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if ( IIRValue == IIR_RLS ) /* Receive Line Status */ |
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{ |
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LSRValue = LPC_UART3->LSR; |
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/* Receive Line Status */ |
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if ( LSRValue & (LSR_OE|LSR_PE|LSR_FE|LSR_RXFE|LSR_BI) ) |
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{ |
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/* There are errors or break interrupt */ |
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/* Read LSR will clear the interrupt */ |
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UART3Status = LSRValue; |
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Dummy = LPC_UART3->RBR; /* Dummy read on RX to clear
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interrupt, then bail out */ |
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return; |
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} |
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if ( LSRValue & LSR_RDR ) /* Receive Data Ready */ |
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{ |
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/* If no error on RLS, normal ready, save into the data buffer. */ |
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/* Note: read RBR will clear the interrupt */ |
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if ((UART3RxQueueWritePos+1) % UARTRXQUEUESIZE != UART3RxQueueReadPos) |
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{ |
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UART3Buffer[UART3RxQueueWritePos] = LPC_UART3->RBR; |
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UART3RxQueueWritePos = (UART3RxQueueWritePos+1) % UARTRXQUEUESIZE; |
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} |
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} |
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LSRValue = LPC_UART3->LSR; |
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/* Receive Line Status */ |
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if ( LSRValue & (LSR_OE|LSR_PE|LSR_FE|LSR_RXFE|LSR_BI) ) |
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{ |
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/* There are errors or break interrupt */ |
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/* Read LSR will clear the interrupt */ |
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UART3Status = LSRValue; |
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dummy = LPC_UART3->RBR; /* Dummy read on RX to clear
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interrupt, then bail out */ |
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return; |
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} |
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if ( LSRValue & LSR_RDR ) /* Receive Data Ready */ |
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{ |
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/* If no error on RLS, normal ready, save into the data buffer. */ |
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/* Note: read RBR will clear the interrupt */ |
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if ((UART3RxQueueWritePos+1) % UARTRXQUEUESIZE != UART3RxQueueReadPos) |
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{ |
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UART3Buffer[UART3RxQueueWritePos] = LPC_UART3->RBR; |
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UART3RxQueueWritePos = (UART3RxQueueWritePos+1) % UARTRXQUEUESIZE; |
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} |
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} |
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} |
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else if ( IIRValue == IIR_RDA ) /* Receive Data Available */ |
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{ |
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/* Receive Data Available */ |
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/* Receive Data Available */ |
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if ((UART3RxQueueWritePos+1) % UARTRXQUEUESIZE != UART3RxQueueReadPos) |
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{ |
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UART3Buffer[UART3RxQueueWritePos] = LPC_UART3->RBR; |
|
|
|
UART3RxQueueWritePos = (UART3RxQueueWritePos+1) % UARTRXQUEUESIZE; |
|
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|
} |
|
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|
else |
|
|
|
dummy = LPC_UART3->RBR;; |
|
|
|
dummy = LPC_UART3->RBR; |
|
|
|
} |
|
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|
else if ( IIRValue == IIR_CTI ) /* Character timeout indicator */ |
|
|
|
{ |
|
|
|
/* Character Time-out indicator */ |
|
|
|
UART3Status |= 0x100; /* Bit 9 as the CTI error */ |
|
|
|
/* Character Time-out indicator */ |
|
|
|
UART3Status |= 0x100; /* Bit 9 as the CTI error */ |
|
|
|
} |
|
|
|
else if ( IIRValue == IIR_THRE ) /* THRE, transmit holding register empty */ |
|
|
|
{ |
|
|
|
/* THRE interrupt */ |
|
|
|
LSRValue = LPC_UART3->LSR; /* Check status in the LSR to see if
|
|
|
|
valid data in U0THR or not */ |
|
|
|
if ( LSRValue & LSR_THRE ) |
|
|
|
{ |
|
|
|
UART3TxEmpty = 1; |
|
|
|
} |
|
|
|
else |
|
|
|
{ |
|
|
|
UART3TxEmpty = 0; |
|
|
|
} |
|
|
|
/* THRE interrupt */ |
|
|
|
LSRValue = LPC_UART3->LSR; /* Check status in the LSR to see if
|
|
|
|
valid data in U0THR or not */ |
|
|
|
if ( LSRValue & LSR_THRE ) |
|
|
|
{ |
|
|
|
UART3TxEmpty = 1; |
|
|
|
} |
|
|
|
else |
|
|
|
{ |
|
|
|
UART3TxEmpty = 0; |
|
|
|
} |
|
|
|
} |
|
|
|
} |
|
|
|
|
|
|
|